參數(shù)資料
型號： S1C6P366D0A0100
元件分類： 微控制器/微處理器
英文描述： 4-BIT, FLASH, 4.1 MHz, MICROCONTROLLER, UUC102
封裝： DIE-102
文件頁數(shù)： 72/84頁
文件大小： 1740K
代理商： S1C6P366D0A0100
64
EPSON
S1C6P366 TECHNICAL MANUAL
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Programmble Timer)
4.9.3.2 Counter mode
The programmable timer can operate in two counter modes, timer mode and event counter mode. It can
be selected by software.
(1) Timer mode
The timer mode counts down using the prescaler output as an input clock. In this mode, the program-
mable timer operates as a periodical timer using the OSC1 or OSC3 oscillation clock as a clock source.
The programmable timer can operate in both the timer mode and the event counter mode. The mode
can be switched using the timer 0 counter mode selection register EVCNT. When the EVCNT register
is set to "0", the programmable timer operates in the timer mode.
At initial reset, this mode is set.
Refer to Section 4.9.3.1, "Setting of initial value and counting down" for basic operation and control.
The input clock in the timer mode is generated by the prescaler built into the programmable timer.
The prescaler generates the input clock by dividing the OSC1 or OSC3 oscillation clock. Refer to the
next section for setting the input clock.
(2) Event counter mode
The programmable timer has an event counter function that counts an external clock input to the
input port K13. This function is selected by writing "1" to the timer 0 counter mode selection register
EVCNT.
In the event counter mode, the clock is supplied to timer 0 from outside of the IC, therefore, the
settings of the timer 0 prescaler division ratio selection registers PTPS00 and PTPS01 and the settings
of the timer 0 source clock selection register CKSEL0 become invalid.
Count down timing can be selected from either the falling or rising edge of the input clock using the
timer 0 pulse polarity selection register PLPOL. When "0" is written to the PLPOL register, the falling
edge is selected, and when "1" is written, the rising edge is selected. The count down timing is shown
in Figure 4.9.3.2.1.
K13 input
Count data
n
n-1
n-2
n-3
n-4
n-5
n-6
PLPOL
EVCNT
01
1
PTRUN0
Fig. 4.9.3.2.1 Timing chart in event counter mode
The event counter mode also includes a noise reject function to eliminate noise such as chattering on
the external clock (K13 input signal). This function is selected by writing "1" to the timer 0 function
selection register FCSEL.
When "with noise rejector" is selected, an input pulse width for both low and high levels must be 0.98
msec or more to count reliably. (The noise rejecter allows the counter to input the clock at the second
falling edge of the internal 2,048 Hz signal after changing the input level of the K13 input port
terminal. Consequently, the pulse width of noise that can reliably be rejected is 0.48 msec or less.)
Figure 4.9.3.2.2 shows the count down timing with noise rejecter.
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