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參數(shù)資料
| 型號： | S1C6P366D0A0100 |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 4-BIT, FLASH, 4.1 MHz, MICROCONTROLLER, UUC102 |
| 封裝： | DIE-102 |
| 文件頁數(shù)： | 59/84頁 |
| 文件大小： | 1740K |
| 代理商： | S1C6P366D0A0100 |
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52
EPSON
S1C6P366 TECHNICAL MANUAL
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (LCD Driver)
4.7.6 I/O memory of LCD driver
Table 4.7.6.1 shows the I/O addresses and the control bits for the LCD driver. Figure 4.7.6.1 shows the
display memory map.
Table 4.7.6.1 Control bits of LCD driver
D3
D2
D1
D0
Name
Init 1
10
Address
Comment
Register
FF60H
LDUTY1 LDUTY0 VCCHG LPWR
R/W
LDUTY1
LDUTY0
VCCHG
LPWR
0
0On
Off
LCD drive duty
switch
General-purpose register (reserved register)
LCD power On/Off
0
1/4
1
1/3
2, 3
1/2
[LDUTY1, 0]
Duty
FF61H
0
ALOFF
ALON
STCD
R
R/W
0 3
ALOFF
ALON
STCD
– 2
1
0
All Off
All On
Static
Normal
Dynamic
Unused
LCD all OFF control
LCD all ON control
Common output signal control
*1 Initial value at initial reset
*2 Not set in the circuit
*3 Constantly "0" when being read
Base address
Low
0
1
234
567
89
A
B
C
D
E
F
F000
F010
Display memory (32 words
× 4 bits) R/W
Fig. 4.7.6.1 Display memory map
LPWR: LCD power control (ON/OFF) register (FF60HD0)
Turns the LCD system voltage circuit ON and OFF.
When "1" is written: ON
When "0" is written: OFF
Reading: Valid
When "1" is written to the LPWR register, the LCD system voltage circuit goes ON and generates the LCD
drive voltage. When "0" is written, all the LCD drive voltages go to VSS level.
It takes about 100 msec for the LCD drive voltage to stabilize after starting up the LCD system voltage
circuit by writing "1" to the LPWR register.
This control does not affect to SEG terminals that have been set for DC output.
At initial reset, this register is set to "0".
LDUTY0, LDUTY1: LCD drive duty switching register (FF60HD2, D3)
Selects the LCD drive duty.
Table 4.7.6.2 Drive duty setting
LDUTY1
1
0
LDUTY0
1
0
Drive duty
1/2
1/3
1/4
Common terminal used
COM0, COM1
COM0–COM2
COM0–COM3
Maximum segment number
64 (32
× 2)
96 (32
× 3)
128 (32
× 4)
Frame frequency
32 Hz
42.7 Hz
32 Hz
When fOSC1 = 32.768 kHz
At initial reset, this register is set to "0".
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