參數(shù)資料
型號(hào)： S1C6P366D0A0100
元件分類： 微控制器/微處理器
英文描述： 4-BIT, FLASH, 4.1 MHz, MICROCONTROLLER, UUC102
封裝： DIE-102
文件頁數(shù)： 27/84頁
文件大?。?/td> 1740K
代理商： S1C6P366D0A0100
S1C6P366 TECHNICAL MANUAL
EPSON
23
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Oscillation Circuit)
4.3.3 OSC3 oscillation circuit
The S1C6P366 has built-in the OSC3 oscillation circuit that generates the CPU's sub-clock for high speed
operation and the source clock for peripheral circuits needing a high speed clock (programmable timer,
FOUT output). The mask option enables selection of either the CR (Typ. 1.8 MHz) or ceramic (Max. 4
MHz ceramic oscillation) oscillation circuit. When CR oscillation is selected, only a resistance is required
as an external element. When ceramic oscillation is selected, a ceramic oscillator and two capacitors (gate
and drain capacitance) are required.
Figure 4.3.3.1 is the block diagram of the OSC3 oscillation circuit.
(a) CR oscillation circuit
(b) Ceramic oscillation circuit
Fig. 4.3.3.1 OSC3 oscillation circuit
As shown in Figure 4.3.3.1, the CR oscillation circuit can be configured simply by connecting the resistor
RCR between the OSC3 and OSC4 terminals when CR oscillation is selected. See Chapter 9, "Electrical
Characteristics" for resistance value of RCR.
When ceramic oscillation is selected, the ceramic oscillation circuit can be configured by connecting the
ceramic oscillator (Max. 4 MHz) between the OSC3 and OSC4 terminals, capacitor CGC between the OSC3
and OSC4 terminals, and capacitor CDC between the OSC4 and VSS terminals. For both CGC and CDC,
connect capacitors that are about 100 pF. To reduce current consumption of the OSC3 oscillation circuit,
oscillation can be stopped by the software (OSCC register).
C CR
OSC3
OSC4
R
CR
VSS
CGC
CDC
Ceramic
OSC4
OSC3
R
RDC
FC
To CPU
(and some peripheral circuits)
Oscillation circuit control signal
To CPU
(and some peripheral circuits)
Oscillation circuit control signal
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