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參數(shù)資料
| 型號： | S1C6P366D0A0100 |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 4-BIT, FLASH, 4.1 MHz, MICROCONTROLLER, UUC102 |
| 封裝： | DIE-102 |
| 文件頁數(shù)： | 50/84頁 |
| 文件大?。?/td> | 1740K |
| 代理商： | S1C6P366D0A0100 |
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44
EPSON
S1C6P366 TECHNICAL MANUAL
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (I/O Ports)
PAD0–PAD3: A/D input channel enable/disable control register (FFD1H)
Selects function for P40–P43.
When "1" is written: A/D converter input
When "0" is written: I/O port
Reading: Valid
When using the A/D converter, write "1" to the register. PAD0–PAD3 correspond to P40–P43, respectively.
When using a port from P40 to P43 as an I/O port, write "0" to the corresponding PAD register.
At initial reset, this register is set to "0".
P00–P03: P0 I/O port data register (FF42H)
P10–P13: P1 I/O port data register (FF46H)
P20–P23: P2 I/O port data register (FF4AH)
P30–P33: P3 I/O port data register (FF4EH)
P40–P43: P4 I/O port data register (FF52H)
I/O port data can be read and output data can be set through these registers.
When writing data
When "1" is written: High level
When "0" is written: Low level
When an I/O port is set to the output mode, the written data is output unchanged from the I/O port
terminal. When "1" is written as the port data, the port terminal goes high (VDD), and when "0" is written,
the terminal goes low (VSS).
Port data can be written also in the input mode.
When reading data
When "1" is read: High level
When "0" is read: Low level
The terminal voltage level of the I/O port is read out. When the I/O port is in the input mode the voltage
level being input to the port terminal can be read out; in the output mode the register value can be read.
When the terminal voltage is high (VDD) the port data that can be read is "1", and when the terminal
voltage is low (VSS) the data is "0".
When the PUL register is set to "1", the built-in pull-up resister goes ON during input mode, so that the I/
O port terminal is pulled up (except for P40–P43).
The data registers of the ports that are set as input/output for the serial interface or A/D converter can be
used as general purpose registers that do not affect the input/output.
Note: When in the input mode, I/O ports are changed from low to high by pull-up resistor, the rise of the
waveform is delayed on account of the time constant of the pull-up resistor and input gate capaci-
tance. Hence, when fetching input ports, set an appropriate wait time.
Particular care needs to be taken of the key scan during key matrix configuration.
Make this waiting time the amount of time or more calculated by the following expression.
10
× C × R
C: terminal capacitance 5 pF + parasitic capacitance ? pF
R: pull-up resistance 300 k
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