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參數(shù)資料
| 型號(hào)： | S1C6P366D0A0100 |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 4-BIT, FLASH, 4.1 MHz, MICROCONTROLLER, UUC102 |
| 封裝： | DIE-102 |
| 文件頁數(shù)： | 29/84頁 |
| 文件大?。?/td> | 1740K |
| 代理商： | S1C6P366D0A0100 |
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S1C6P366 TECHNICAL MANUAL
EPSON
25
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Oscillation Circuit)
4.3.7 I/O memory of oscillation circuit
Table 4.3.7.1 shows the I/O address and the control bits for the oscillation circuit.
Table 4.3.7.1 Control bits of oscillation circuit
Address
Comment
D3
D2
Register
D1
D0
Name
Init 1
10
FF00H
CLKCHG OSCC
0
VDC
R
R/W
CLKCHG
OSCC
0 3
VDC
0
– 2
0
OSC3
On
(OSC3)
OSC1
Off
(OSC1)
CPU clock switch
OSC3 oscillation On/Off
Unused
(Operating voltage switch)
*1 Initial value at initial reset
*2 Not set in the circuit
*3 Constantly "0" when being read
VDC: Operating voltage switching register (FF00HD0)
In the S1C6P366, the value set in this register does not affect the VD1 voltage level. However, note that the
register value affects the CLKCHG register that switches the CPU clock.
When using the S1C6P366 as a development tool for the S1C63358/63158, switch the operating voltage
using this register according to the control sequence of the model (refer to the "Technical Manual").
At initial reset, this register is set to "0".
OSCC: OSC3 oscillation control register (FF00HD2)
Controls oscillation ON/OFF for the OSC3 oscillation circuit.
When "1" is written: OSC3 oscillation ON
When "0" is written: OSC3 oscillation OFF
Reading: Valid
When it is necessary to operate the CPU at high speed, set OSCC to "1". At other times, set it to "0" to
reduce current consumption.
At initial reset, this register is set to "0".
CLKCHG: CPU system clock switching register (FF00HD3)
The CPU's operation clock is selected with this register.
When "1" is written: OSC3 clock is selected
When "0" is written: OSC1 clock is selected
Reading: Valid
When the CPU clock is to be OSC3, set CLKCHG to "1"; for OSC1, set CLKCHG to "0".
After turning the OSC3 oscillation ON (OSCC = "1"), switching of the clock should be done after waiting
5 msec or more.
When VDC = "0" and/or when OSC3 oscillation is OFF (OSCC = "0"), setting of CLKCHG = "1" becomes
invalid and switching to OSC3 is not performed.
At initial reset, this register is set to "0".
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