- 您現(xiàn)在的位置：買(mǎi)賣IC網(wǎng) > PDF目錄98068 > S1C63406D0A0100 MICROCONTROLLER, UUC103 PDF資料下載
參數(shù)資料
| 型號(hào)： | S1C63406D0A0100 |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | MICROCONTROLLER, UUC103 |
| 封裝： | DIE-103 |
| 文件頁(yè)數(shù)： | 89/151頁(yè) |
| 文件大?。?/td> | 1171K |
| 代理商： | S1C63406D0A0100 |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)當(dāng)前第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)第127頁(yè)第128頁(yè)第129頁(yè)第130頁(yè)第131頁(yè)第132頁(yè)第133頁(yè)第134頁(yè)第135頁(yè)第136頁(yè)第137頁(yè)第138頁(yè)第139頁(yè)第140頁(yè)第141頁(yè)第142頁(yè)第143頁(yè)第144頁(yè)第145頁(yè)第146頁(yè)第147頁(yè)第148頁(yè)第149頁(yè)第150頁(yè)第151頁(yè)
34
EPSON
S1C63406/408 TECHNICAL MANUAL
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Input Ports)
KCP00–KCP03: K0 port input comparison register (FF55H)
Interrupt conditions for terminals K00–K03 can be set with these registers.
When "1" is written: Falling edge
When "0" is written: Rising edge
Reading: Valid
The interrupt conditions can be set for the rising or falling edge of input for each of the four bits (K00–
K03), through the input comparison registers (KCP00–KCP03).
A comparison is done only with the ports that are enabled by the interrupt among K00–K03 by means of
the SIK00–SIK03 registers.
At initial reset, these registers are set to "1".
K0NR0, K0NR1: K0 interrupt noise rejector selection register (FF43HD0, D1)
Selects the noise-reject width.
Table 4.4.4.2 Setting up noise rejector
K0NR1
1
0
K0NR0
1
0
1
0
Noise-reject width
7.8 msec
2.0 msec
0.5 msec
OFF (bypassed)
(When fOSC1 = 32.768 kHz)
Be sure to turn the noise rejector OFF before executing the SLP instruction.
At initial reset, these registers are set to "0".
EIK00–EIK03: K0 input interrupt mask register (FFEBH)
Masks the input interrupt request to the CPU.
When "1" is written: Enable
When "0" is written: Mask
Reading: Valid
When "1" is written to the EIK0x register, the input interrupt request will be generated to the CPU. When
"0" is written, no input interrupt will be generated from the corresponding port.
The wake up signal to release the SLEEP mode will be generated even if this register is set to "0". How-
ever, enable the input port interrupt using the corresponding interrupt mask register before executing the
SLP instruction to run input interrupt handler routine after SLEEP status is released.
At initial reset, this register is set to "0".
IK00–IK03: K0 input interrupt factor flag (FFFBH)
This flag indicates the occurrence of input interrupt.
When "1" is read: Interrupt has occurred
When "0" is read: Interrupt has not occurred
When "1" is written: Flag is reset
When "0" is written: Invalid
IK0x is the interrupt factor flag corresponding to the K0x port. From the status of this flag, the software
can decide whether an input interrupt has occurred.
The interrupt factor flag is set to "1" when the interrupt condition is established regardless of the interrupt
mask register setting. However, the interrupt does not occur to the CPU when the interrupt is masked.
This flag is reset to "0" by writing "1".
After an interrupt occurs, the same interrupt will occur again if the interrupt enabled state (I flag = "1") is
set or the RETI instruction is executed unless the interrupt factor flag is reset. Therefore, be sure to reset
(write "1" to) the interrupt factor flag in the interrupt service routine before shifting to the interrupt
enabled state.
At initial reset, this flag is set to "0".
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| S1C63455F | 4-BIT, MROM, 4.1 MHz, MICROCONTROLLER, PQFP128 |
| S1C63455D | 4-BIT, MROM, 4.1 MHz, MICROCONTROLLER, UUC105 |
| S1C63458F0A0100 | MICROCONTROLLER, PQFP144 |
| S1C63466D | 4-BIT, MROM, 4.1 MHz, MICROCONTROLLER, UUC140 |
| S1C63466F | 4-BIT, MROM, 4.1 MHz, MICROCONTROLLER, PQFP144 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| S1C63408 | 制造商:EPSON 制造商全稱:EPSON 功能描述:4-bit Single Chip Microcomputer |
| S1C63557D04Q000 | 制造商:Seiko Instruments Inc (SII) 功能描述:EPSON MCU 4BIT |
| S1C63567 | 制造商:EPSON 制造商全稱:EPSON 功能描述:4-bit Single Chip Microcomputer |
| S1C63616 | 制造商:EPSON 制造商全稱:EPSON 功能描述:4-bit Single Chip Microcomputer |
| S1C63632 | 制造商:EPSON 制造商全稱:EPSON 功能描述:4-bit Single Chip Microcomputer |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。