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參數(shù)資料
| 型號(hào)： | S1C63406D0A0100 |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | MICROCONTROLLER, UUC103 |
| 封裝： | DIE-103 |
| 文件頁(yè)數(shù)： | 36/151頁(yè) |
| 文件大?。?/td> | 1171K |
| 代理商： | S1C63406D0A0100 |
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122
EPSON
S1C63406/408 TECHNICAL MANUAL
CHAPTER 7: ELECTRICAL CHARACTERISTICS
Current consumption
Item
Current consumption
during SLEEP
Current consumption
during HALT
Current consumption
during execution
(software duty = 100%)
Heavy load protection
current
Current consumption
in reset status
LCD circuit current
SVD circuit curent
Reset circuit current
1
2
3
4
5
6
7
Symbol
ISLP
IHALT1
IHALT2
IHALT3
IEXE
IHVLD
IRSTON
ILCD1
ILCD2
ISVD
IRST
Unit
A
Max.
2.5
2.6
6
5
7
13
10
7
7.5
8
5
10
200
400
700
1000
1200
45
25
4
3
7
4
Typ.
1.2
1.3
3.0
2.5
3.5
6.2
4.6
3.2
3.5
3.8
3.0
7.0
90
200
350
500
550
30
17
1.7
1.2
5.5
2.5
Min.
OSC1=ON (clock is not supplied to the divider and peripheral circuit), OSC3=OFF, CPU clock=OSC1, SVD=OFF,
reset circuit is not selected
OSC1=ON, OSC3=OFF, CPU clock=OSC1, SVD=OFF, reset circuit is not selected
OSC1=ON, OSC3=OFF, CPU clock=OSC1, SVD=OFF, reset circuit is selected
OSC1=ON, OSC3=ON, CPU clock=OSC3, SVD=OFF, reset circuit is not selected
Reset status due to supply voltage detection by the reset circuit, OSC1=ON, OSC3=ON, CPU clock=OSC3, SVD=OFF,
reset circuit is selected, LCD OFF, higher VDD increases current consumption.
When LPWR = "1", current consumption is increased for a cycle of 2 kHz, then it is decreased and stabilized. Also current
consumption of the LCD circuit varies according to the OSC1 clock frequency.
Current consumption of the reset circuit varies slightly depending on the option selected. The table lists the values when
1.4 V option is selected (1.4 V option has the largest current consumption under the same VDD conditions).
Condition
OSC1=32kHz crystal
LCD off
1
OSC1=32kHz crystal
LCD off
2
LCD on (VC1 std.)
2
LCD on (VC2 std.)
2
OSC1=60kHz CR
LCD off
2
LCD on (VC1 std.)
2
LCD on (VC2 std.)
2
OSC1=32kHz crystal
Reset circuit (1.8V option)
3
LCD off
Reset circuit (1.6V option)
3
Reset circuit (1.4V option)
3
OSC1=32kHz crystal
LCD off
2
OSC1=60kHz CR
LCD off
2
OSC3=500kHz CR
LCD off
4
OSC3=1MHz CR
LCD off
4
OSC3=2MHz CR
LCD off
4
OSC3=3.58MHz ceramic
LCD off
4
OSC3=4MHz crystal
LCD off
4
OSC1=32kHz crystal, LCD off, HLMOD register="1"
2
OSC1=32kHz crystal, VDD=1.29V,
5
when reset circuit option is selected
VDD=3.6V, VC1 standard, fOSC1=32.768kHz
6
VDD=3.6V, VC2 standard, fOSC1=32.768kHz
6
VDD=1.3 to 3.6V, during supply voltage detection
VDD=3.6V
7
Unless otherwise specified: VDD=3.6V, VSS=0V, Ta=25
°C, VD1/VOSC/VC1/VC2/VC4/VC5 are internal voltage, C1–C8=0.1F,
No panel load, Not in heavy load protection mode
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