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EPSON
S1C63406/408 TECHNICAL MANUAL
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Memory Map)
CHAPTER
4 PERIPHERAL CIRCUITS AND OPERATION
The peripheral circuits of S1C63406/408 (timer, I/O, etc.) are interfaced with the CPU in the
memory mapped I/O method. Thus, all the peripheral circuits can be controlled by accessing the I/O
memory on the memory map using the memory operation instructions. The following sections explain
the detailed operation of each peripheral circuit.
4.1 Memory Map
The S1C63406 data memory consists of 1,024-word RAM, 3,072-word data ROM, 540-bit display memory
and 50-word peripheral I/O memory.
The S1C63408 data memory consists of 1,024-word RAM, 4,096-word data ROM, 1,020-bit display
memory and 50-word peripheral I/O memory.
Figure 4.1.1 shows the overall memory map of the S1C63406/408, and Tables 4.1.1(a)–(d) the peripheral
circuits' (I/O space) memory maps.
S1C63406
0000H
0400H
8000H
8C00H
F000H
FF00H
FFFFH
RAM area
Unused area
Data ROM area
I/O memory area
Display memory area
Unused area
Peripheral I/O area
F000H
F177H
FF00H
FF80H
FFC0H
FFFFH
S1C63408
0000H
0400H
8000H
9000H
F000H
FF00H
FFFFH
RAM area
Unused area
Data ROM area
I/O memory area
Display memory area
Unused area
Peripheral I/O area
F000H
F277H
FF00H
FF80H
FFC0H
FFFFH
Fig. 4.1.1 Memory map
Note: Memory is not implemented in unused areas within the memory map. Further, some non-imple-
mentation areas and unused (access prohibition) areas exist in the display memory area and the
peripheral I/O area. If the program that accesses these areas is generated, its operation cannot be
guaranteed. Refer to Section 4.7.4, "Display memory", for the display memory, and the I/O memory
maps shown in Tables 4.1.1 (a)–(d) for the peripheral I/O area.