S1C63406/408 TECHNICAL MANUAL
EPSON
95
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Serial Interface)
ESIF: Serial interface enable register (P2 port function selection) (FF70HD0)
Sets P20–P23 to the input/output port for the serial interface.
When "1" is written: Serial interface
When "0" is written: I/O port
Reading: Valid
The ESIF is the serial interface enable register and P20–P23 terminals become serial input/output termi-
nals (SIN, SOUT, SCLK, SRDY) when "1" is written, and they become I/O port terminals when "0" is
written.
Also, see Table 4.11.3.2 for the terminal settings according to the transfer modes.
At initial reset, this register is set to "0".
PPL20: SIN pull-up control register (FF49HD0)
PPL22: SCLK pull-up control register (FF49HD2)
Sets the pull-up of the SIN terminal and the SCLK terminals (in the slave mode).
When "1" is written: Pull-up ON
When "0" is written: Pull-up OFF
Reading: Valid
Sets the pull-up resistor built into the SIN (P20) and SCLK (P22) terminals to ON or OFF.
SCLK pull-up is effective only in the slave mode. In the master mode, the PPL22 register can be used as a
general purpose register.
At initial reset, these registers are set to "1" and the lines are pulled up.
SMD0, SMD1: Serial interface mode selection register (FF70HD1, D2)
Set the transfer modes as shown in Table 4.11.9.2.
Table 4.11.9.2 Transfer mode settings
SMD1
SMD0
Mode
1
0
1
0
1
0
8-bit asynchronous
7-bit asynchronous
Clock synchronous slave
Clock synchronous master
SMD0 and SMD1 can also read out.
At initial reset, this register is set to "0".
SCS0, SCS1: Clock source selection register (FF71HD0, D1)
Select the clock source as shown in Table 4.11.9.3.
Table 4.11.9.3 Clock source selection
SCS1
1
0
SCS0
1
0
1
0
Clock source
Programmable timer
fOSC3 / 93
fOSC3 / 372
fOSC3 / 186
SCS0 and SCS1 can also be read out.
In the clock synchronous slave mode, setting of this register is invalid.
At initial reset, this register is set to "0".