- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄98068 > S1C63406D0A0100 MICROCONTROLLER, UUC103 PDF資料下載
參數(shù)資料
| 型號(hào)： | S1C63406D0A0100 |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | MICROCONTROLLER, UUC103 |
| 封裝： | DIE-103 |
| 文件頁數(shù)： | 10/151頁 |
| 文件大小： | 1171K |
| 代理商： | S1C63406D0A0100 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁當(dāng)前第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁第125頁第126頁第127頁第128頁第129頁第130頁第131頁第132頁第133頁第134頁第135頁第136頁第137頁第138頁第139頁第140頁第141頁第142頁第143頁第144頁第145頁第146頁第147頁第148頁第149頁第150頁第151頁
S1C63406/408 TECHNICAL MANUAL
EPSON
99
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Serial Interface)
EISRC, EISTR, EISER: Interrupt mask registers (FFE3HD0, D1, D2)
Enables or disables the generation of an interrupt for the CPU.
When "1" is written: Enabled
When "0" is written: Disabled
Reading: Valid
EISRC, EISTR and EISER are interrupt mask registers that respectively correspond to the interrupt factors
for receivie completion, transmit completion and receive error. Interrupts set to "1" are enabled and
interrupts set to "0" are disabled.
At initial reset, these registers are set to "0".
ISRC, ISTR, ISER: Interrupt factor flags (FFF3HD0, D1, D2)
Indicates the serial interface interrupt generation status.
When "1" is read: Interrupt has occurred
When "0" is read: Interrupt has not occurred
When "1" is written: Flag is reset
When "0" is written: Invalid
ISRC, ISTR and ISER are interrupt factor flags that respectively correspond to the interrupts for receivie
completion, transmit completion and receive error, and are set to "1" by generation of each factor.
Transmit completion interrupt factor is generated at the point where the data transmition of the shift
register has been completed.
Receive completion interrupt factor is generated at the point where the received data has been transferred
into the receive data buffer.
Receive error interrupt factor is generated when a parity error, framing error or overrun error has been
detected during data receiving.
When set in this manner, if the corresponding interrupt enable mask is set to "1" and the CPU is set to
interrupt enabled status (I flag = "1"), an interrupt will be generated to the CPU.
Regardless of the interrupt mask register setting, the interrupt factor flag will be set to "1" by the occurrence
of an interrupt generation condition.
The interrupt factor flag is reset to "0" by writing "1".
After an interrupt occurs, the same interrupt will occur again if the interrupt enabled state (I flag = "1") is
set or the RETI instruction is executed unless the interrupt factor flag is reset. Therefore, be sure to reset
(write "1" to) the interrupt factor flag in the interrupt service routine before shifting to the interrupt
enabled state.
At initial reset, these flags are set to "0".
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| S1C63455F | 4-BIT, MROM, 4.1 MHz, MICROCONTROLLER, PQFP128 |
| S1C63455D | 4-BIT, MROM, 4.1 MHz, MICROCONTROLLER, UUC105 |
| S1C63458F0A0100 | MICROCONTROLLER, PQFP144 |
| S1C63466D | 4-BIT, MROM, 4.1 MHz, MICROCONTROLLER, UUC140 |
| S1C63466F | 4-BIT, MROM, 4.1 MHz, MICROCONTROLLER, PQFP144 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| S1C63408 | 制造商:EPSON 制造商全稱:EPSON 功能描述:4-bit Single Chip Microcomputer |
| S1C63557D04Q000 | 制造商:Seiko Instruments Inc (SII) 功能描述:EPSON MCU 4BIT |
| S1C63567 | 制造商:EPSON 制造商全稱:EPSON 功能描述:4-bit Single Chip Microcomputer |
| S1C63616 | 制造商:EPSON 制造商全稱:EPSON 功能描述:4-bit Single Chip Microcomputer |
| S1C63632 | 制造商:EPSON 制造商全稱:EPSON 功能描述:4-bit Single Chip Microcomputer |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。