參數(shù)資料
型號: S1C63406D0A0100
元件分類: 微控制器/微處理器
英文描述: MICROCONTROLLER, UUC103
封裝: DIE-103
文件頁數(shù): 41/151頁
文件大小: 1171K
代理商: S1C63406D0A0100
S1C63406/408 TECHNICAL MANUAL
EPSON
127
CHAPTER 7: ELECTRICAL CHARACTERISTICS
Asynchronous system
Item
Start bit detection error time
1
Erroneous start bit detection range time
2
1
2
Symbol
tsa1
tsa2
Unit
s
Max.
t/16
10
t/16
Typ.
Min.
0
9
t/16
Start bit detection error time is a logical delay time from inputting the start bit until internal sampling begins operating.
(Time as far as AC is excluded.)
Erroneous start bit detection range time is a logical range to detect whether a LOW level (start bit) has been input again
after a start bit has been detected and the internal sampling clock has started. When a HIGH level is detected, the start bit
detection circuit is reset and goes into a wait status until the next start bit. (Time as far as AC is excluded.)
Condition: VDD=1.4 to 3.6V, VSS=0V, Ta=-40 to 85
°C
tsa1
t
tsa2
SIN
Start bit
Sampling
clock
Erroneous
start bit
detection signal
Stop bit
7.7 Timing Chart
System clock switching
VDC1, 0
OSCC
CLKCHG
2.5 msec min.
5 msec min.
1 instruction execution time or longer
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