參數(shù)資料
型號: S1C621A0F0A0100
元件分類: 微控制器/微處理器
英文描述: MICROCONTROLLER, PQFP80
封裝: QFP-80
文件頁數(shù): 71/161頁
文件大小: 1037K
代理商: S1C621A0F0A0100
163
32000D–04/2011
AVR32
DIVS – Signed divide
Architecture revision:
Architecture revision1 and higher.
Description
Performs a signed divide between the two 32-bit register specified. The quotient is returned in
Rd, the remainder in Rd+1. No exceptions are taken if dividing by 0. Result in Rd and Rd+1 is
UNDEFINED when dividing by 0. The sign of the remainder will be the same as the dividend,
and the quotient will be negative if the signs of Rx and Ry are opposite.
Operation:
I.
Rd
← Rx / Ry;
Rd+1
← Rx % Ry;
Syntax:
I.
divs
Rd, Rx, Ry
Operands:
I.
d
∈ {0, 2, …, 14}
{x, y}
∈ {0, 1, …, 15}
Status Flags
Q:
Not affected
V:
Not affected
N:
Not affected
Z:
Not affected
C:
Not affected
Opcode:
111
Rx
00000
Ry
31
29
28
25
24
20
19
16
000011000000
Rd
15
12
11
4
3
0
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