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| 型號： | S1C60A13F |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 4-BIT, MROM, 1.2 MHz, MICROCONTROLLER, PQFP80 |
| 封裝： | PLASTIC, QFP14-80 |
| 文件頁數(shù)： | 89/104頁 |
| 文件大小： | 850K |
| 代理商： | S1C60A13F |
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S1C60N13 TECHNICAL MANUAL
EPSON
77
CHAPTER 5: SUMMARY OF NOTES
When using an input interrupt, if you rewrite the content of the mask register, when the value of the
input terminal which becomes the interrupt input is in the active status, the factor flag for input
interrupt may be set.
Therefore, when using the input interrupt, the active status of the input terminal implies
input terminal = low status, when the falling edge interrupt is effected and
input terminal = high status, when the rising edge interrupt is effected.
When an interrupt is triggered at the falling edge of an input terminal, a factor flag is set with the
timing of shown in Figure 5.2.1. However, when clearing the content of the mask register with the
input terminal kept in the low status and then setting it, the factor flag of the input interrupt is again
set at the timing that has been set.
Consequently, when the input terminal is in the active status (low status), do not rewrite the mask
register (clearing, then setting the mask register), so that a factor flag will only set at the falling edge
in this case. When clearing, then setting the mask register, set the mask register, when the input
terminal is not in the active status (high status).
When an interrupt is triggered at the rising edge of the input terminal, a factor flag will be set at the
timing of shown in Figure 5.2.1. In this case, when the mask registers cleared, then set, you should
set the mask register, when the input terminal is in the low status.
In addition, when the mask register = "1" and the content of the input comparison register is rewritten
in the input terminal active status, an input interrupt factor flag may be set. Thus, you should rewrite
the content of the input comparison register in the mask register = "0" status.
Output port
When BZ, BZ and FOUT are selected with the mask option, a hazard may be observed in the output
waveform when the data of the output register changes.
I/O port
(1) When input data are changed from high to low by built-in pull-down resistance, the fall of the
waveform is delayed on account of the time constant of the pull-down resistance and input gate
capacitance. Consequently, if data is read out while the CPU is running in the OSC3 oscillation circuit,
data must be read out continuously for about 500 sec.
(2) When the I/O port is set to the output mode and the data register has been read, the terminal data
instead of the register data can be read out. Because of this, if a low-impedance load is connected and
read-out performed, the value of the register and the read-out result may differ.
Serial interface
(1) If the bit data of SE2 changes while SCLK is in the master mode, a hazard will be output to the SCLK
pin. If this poses a problem for the system, be sure to set the SCLK to the external clock if the bit data
of SE2 is to be changed.
(2) Be sure that read-out of the interrupt factor flag (ISIO) is done only when the serial port is in the STOP
status (SIOF = "0") and the DI status (interrupt flag = "0"). If read-out is performed while the serial
data is in the RUN status (during input or output), the data input or output will be suspended and the
initial status resumed. Read-out during the EI status (interrupt flag = "1") causes malfunctioning.
(3) When using the serial interface in the master mode, the synchronous clock uses the CPU system clock.
Accordingly, do not change the system clock (fOSC1
fOSC3) while the serial interface is operating.
(4) Perform data writing/reading to data registers SD0–SD7 only while the serial interface is halted (i.e.,
the synchronous clock is neither being input or output).
(5) As a trigger condition, it is required that data writing or reading on data registers SD0–SD7 be per-
formed prior to writing "1" to SCTRG. (The internal circuit of the serial interface is initiated through
data writing/reading on data registers SD0–SD7.) Supply trigger only once every time the serial
interface is placed in the RUN state. Moreover, when the synchronous clock SCLK is external clock,
start to input the external clock after the trigger.
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