
S1C60N13 TECHNICAL MANUAL
EPSON
63
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Event Counter)
EV1RST: Event counter 1 reset (2FCHD1)
This is the register for resetting event counter 1.
When "1" is written : Event counter 1 reset
When "0" is written : No operation
Read-out : Always "0"
When "1" is written, event counter 1 is reset and the data becomes "00H". When "0" is written, no opera-
tion is executed.
This is a write-only bit, and is always "0" at read-out.
EVRUN: Event counter RUN/STOP (2FCHD2)
This register controls the event counter RUN/STOP status.
When "1" is written : RUN
When "0" is written : STOP
Read-out : Valid
When "1" is written, the event counter enters the RUN status and starts receiving the clock signal input.
When "0" is written, the event counter enters the STOP status and the clock signal input is ignored.
(However, input to the input port is valid.)
At initial reset, this register is set to "0".
EVSEL: Event counter mode (2FCHD3)
This register control the count mode of the event counter.
When "1" is written : Separate
When "0" is written : Phase detection
Read-out : Valid
When "0" is written, the phases of the two clock signals are detected, and the phase detection mode is
selected, in which one of the counters is chosen to input the clock signal. When "1" is written, the separate
mode is selected, in which each clock signal is input to different counters.
At initial reset, this register is set to "0".
4.12.5 Programming notes
(1) After the event counter has written data to the EVRUN register, it operates or stops in synchroniza-
tion with the falling edge of the noise rejector clock or stops. Hence, attention must be paid to the
above timing when input signals (input to K02 and K03) are being received.
(2) To prevent erroneous reading of the event counter data, read out the counter data several times,
compare it, and use the matching data as the result.