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EPSON
S1C60N13 TECHNICAL MANUAL
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Input Ports)
4.4.4 Control of input ports
Table 4.4.4.1 lists the input ports control bits and their addresses.
Table 4.4.4.1 Input port control bits
Address
Comment
D3
D2
Register
D1
D0
Name
Init 1
10
2E3H
K03
K02
K01
K00
R
K03
K02
K01
K00
– 2
High
Low
Input port data (K00–K03)
2E5H
EIK03
EIK02
EIK01
EIK00
R/W
EIK03
EIK02
EIK01
EIK00
0
Enable
Mask
Interrupt mask register (K00–K03)
2E4H
KCP03
KCP02
KCP01
KCP00
R/W
KCP03
KCP02
KCP01
KCP00
0
Input comparison register (K00–K03)
2E7H
SCTRG
EIK10
KCP10
K10
WR
R/W
SCTRG
3
EIK10
KCP10
K10
–
0
– 2
Trigger
Enable
High
–
Mask
Low
Serial I/F clock trigger
Interrupt mask register (K10)
Input comparison register (K10)
Input port data (K10)
2EAH
IK1
IK0
SWIT1
SWIT0
R
IK1 4
IK0 4
SWIT1 4
SWIT0 4
0
Yes
No
Interrupt factor flag (K10)
Interrupt factor flag (K00–K03)
Interrupt factor flag (stopwatch 1 Hz)
Interrupt factor flag (stopwatch 10 Hz)
1
2
Initial value at initial reset
Not set in the circuit
3
4
Always "0" being read
Reset (0) immediately after being read
5 Undefined
K00–K03, K10: Input port data (2E3H, 2E7HD0)
Input data of the input port terminals can be read out with these registers.
When "1" is read out : High level
When "0" is read out : Low level
Writing : Invalid
The read-out is "1" when the terminal voltage of the five bits of the input ports (K00–K03, K10) goes high
(VDD), and "0" when the voltage goes low (VSS).
These bits are dedicated for read-out, so writing cannot be done.
KCP00–KCP03, KCP10: Input comparison registers (2E4H, 2E7HD1)
Interrupt conditions for terminals K00–K03 and K10 can be set with these registers.
When "1" is written : Falling edge
When "0" is written : Rising edge
Read-out : Valid
The interrupt conditions can be set for the rising or falling edge of input for each of the five bits (K00–K03
and K10), through the input comparison registers (KCP00–KCP03 and KCP10).
At initial reset, these registers are set to "0".
EIK00–EIK03, EIK10: Interrupt mask registers (2E5H, 2E7HD2)
Masking the interrupt of the input port terminals can be selected with these registers.
When "1" is written : Enable
When "0" is written : Mask
Read-out : Valid
With these registers, masking of the input port bits can be selected for each of the five bits.
Writing to the interrupt mask registers can be done only in the DI status (interrupt flag = "0").
At initial reset, these registers are all set to "0".