參數(shù)資料
型號(hào)： S1C60A13F
元件分類： 微控制器/微處理器
英文描述： 4-BIT, MROM, 1.2 MHz, MICROCONTROLLER, PQFP80
封裝： PLASTIC, QFP14-80
文件頁(yè)數(shù)： 40/104頁(yè)
文件大小： 850K
代理商： S1C60A13F
32
EPSON
S1C60N13 TECHNICAL MANUAL
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Serial Interface)
4.7 Serial Interface
4.7.1 Configuration of serial interface
The S1C60N13 Series has a built-in synchronous clock type 8 bits serial interface that can be enabled by
mask option. The configuration of the serial interface is shown in Figure 4.7.1.1.
The CPU, via the 8 bits shift register, can read the serial input data from the SIN (P10) terminal. Moreover,
via the same 8 bits shift register, it can convert parallel data to serial data and output it to the SOUT (P11)
terminal. The synchronous clock for serial data input/output may be set by selecting by software any one
of 3 types of master mode (internal clock mode: when the S1C60N13 Series is to be the master for serial
input/output) and a type of slave mode (external clock mode: when the S1C60N13 Series is to be the
slave for serial input/output).
Also, when the serial interface is used at slave mode, SIOF (R11) signal which indicates whether or not
the serial interface is available to transmit or receive can be output to output port R11 by mask option.
SD0–SD7
SCS0
SCS1
SE2
Output
latch
EISIO
Serial I/F
interrupt control
circuit
ISIO
SIOF
(R11)
SCTRG
Serial I/F
activating
circuit
System clock
Serial clock
counter
Serial clock
selector
Shift register (8 bits)
Serial clock
generator
SOUT
(P11)
SIN
(P10)
SCLK
(P12)
Fig. 4.7.1.1 Configuration of serial interface
The SIN (P10) and SCLK (P12) terminals have a pull-down resistor. However, the SCLK (P12) terminal is
pulled down to low in external clock mode and the pull-down resistor is disabled in internal clock mode.
4.7.2 Mask option
The serial interface may be selected for the following by mask option.
(1) Whether the serial interface is used or not may be selected. When "use" is selected, the following I/O
port terminals are configured as the serial I/O terminals.
P10
→ SIN (data input)
P11
→ SOUT (data output)
P12
→ SCLK (clock input/output)
(2) Either complementary output or Pch open drain as output specification for the SOUT (P11) terminal
may be selected. However, even if Pch open drain has been selected, application of voltage exceeding
power source voltage to the SOUT (P11) terminal will be prohibited.
(3) As output specification during output mode, either complementary output or Pch open drain output
may be selected for the SCLK (P12) terminal.
(4) Positive or negative logic can be selected for the signal logic of the SIO function. However, keep in
mind that only pull-down resistance can be set for the input mode (pull-up resistance is not built-in).
(5) LSB first or MSB first as input/output permutation of serial data may be selected in the SIO function.
(6) Output port R11 may be assigned as SIOF (R11) output terminal which will indicate whether the serial
interface is available to transmit or receive signals.
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