
S1C60N13 TECHNICAL MANUAL
EPSON
69
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Interrupt and HALT)
4.16 Interrupt and HALT
The S1C60N13 Series provides the following interrupt settings, each of which is maskable.
External interrupt:
Input interrupt (two)
Internal interrupt:
Timer interrupt (three)
Stopwatch interrupt (two)
Serial interface interrupt (one)
To authorize interrupt, the interrupt flag must be set to "1" (EI) and the necessary related interrupt mask
registers must be set to "1" (enable).
When an interrupt occurs the interrupt flag is automatically reset to "0" (DI), and interrupts after that are
inhibited.
When a HALT instruction is input the CPU operating clock stops, and the CPU enters the HALT status.
The CPU is reactivated from the HALT status when an interrupt request occurs.
If reactivation is not caused by an interrupt request, initial reset by the watchdog timer causes reactivates
the CPU (when the watchdog timer is enabled).
Figure 4.16.1 shows the configuration of the interrupt circuit.
Interrupt vector map
Table 4.16.1 Interrupt vector map
Page
1
Step
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
Interrupt vector
Initial reset
Serial interface interrupt
Input port interrupt
Serial interface + Input port interrupt
Clock timer interrupt
Serial interface + Clock timer interrupt
Input port + Clock timer interrupt
Serial interface + Input port + Clock timer interrupt
Stopwatch timer interrupt
Serial interface + Stopwatch timer interrupt
Input port + Stopwatch timer interrupt
Serial interface + Input port + Stopwatch timer interrupt
Clock timer + Stopwatch timer interrupt
Serial interface + Clock timer + Stopwatch timer interrupt
Input port + Clock timer + Stopwatch timer interrupt
All interrupts
The interrupt service routine start address should be written to each interrupt vector address.