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參數(shù)資料
| 型號： | PNX8511 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Analog companion chip |
| 中文描述： | 模擬伴隨芯片 |
| 文件頁數(shù)： | 60/92頁 |
| 文件大?。?/td> | 3064K |
| 代理商： | PNX8511 |
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Philips Semiconductors
PNX8510/11
Analog companion chip
Product data
Rev. 04 – 12 January 2004
60 of 92
9397 750 12612
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
8.2 Audio/Clock Address Space
Offset 0xC7 - HD_GAIN_RY(HD Data Path)*
7:0
HD_GAIN_R/Y
R/W
0x00
Gain adjust for R/Y component in HD-RGB/YUV data path, two’s
complement number to adjust the gain from 1-0.5 to 1+-0.5
out=in x (1+ GAIN/256)
Offset 0xC8 - HD_GAIN_GU(HD Data Path)*
7:0
HD_GAIN_G/U
R/W
0x00
Gain adjust for G/U component in HD-RGB/YUV data path, two’s
complement number to adjust the gain from 1-0.5 to 1+-0.5
out=in x (1+ GAIN/256)
Offset 0xC9 - HD_GAIN_BV(HD Data Path)*
7:0
HD_GAIN_B/V
R/W
0x00
Gain adjust for B/V component in HD-RGB/YUV data path, two’s
complement number to adjust the gain from 1-0.5 to 1+-0.5
out=in x (1+ GAIN/256)
Table 29:
* indicates not present in secondary video channel
Bit
Symbol
PNX8510/11 video registers
…continued
Access Value
Description
Table 30:
Bit
Offset 0000 - CLK_AUDIO
7:1
Unused
0
CLK_AUDIO
PNX8510/11 Audio/Clock Registers
Symbol
Access
Value
Description
-
0
R/W
0 = I
2
S is in slave mode.
1 = I
2
S is in master mode.
Offset 0001 - CLK_IF Video Interface Clock
7:5
Unused
4
CLK_IF_DIV8
-
0
R/W
0 = default (divide by 4).
1 = divide by 8.
0 = default (divide by 3).
1 = divide by 6.
00 = clk_if is input video clock divide by 1 (feed through).
01 = clk_if is input video clock divide by 2.
10 = clk_if is input video clock divide by 3/6.
11 = clk_if is input video clock divide by 4/8.
0 = Normal functional mode
1 = Set the clock to zero.
3
CLK_IF_DIV6
R/W
0
2:1
CLK_IF_DIV
R/W
0x0
0
CLK_IF_EN
R/W
0
Offset 0002 - CLK_PROC_DIV Video Processing Clock
7:5
Unused
4
CLK_PROC_DIV8
-
0
R/W
0 = Divide by 4.
1 = Divide by 8.
0 = Default (div.ide by 3).
1 = Divide by 6
00 = clk_proc is input video clock divide by 1 (feed through).
01 = clk_proc is input video clock divide by 2.
10 = clk_proc is input video clock divide by 3/6.
11 = clk_proc is input video clock divide by 4/8.
3
CLK_PROC_DIV6
R/W
0
2:1
CLK_PROC_DIV
R/W
0x0
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