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參數(shù)資料
| 型號： | PNX8511 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Analog companion chip |
| 中文描述： | 模擬伴隨芯片 |
| 文件頁數(shù)： | 38/92頁 |
| 文件大?。?/td> | 3064K |
| 代理商： | PNX8511 |
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Philips Semiconductors
PNX8510/11
Analog companion chip
Product data
Rev. 04 – 12 January 2004
38 of 92
9397 750 12612
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
The PNX8510/11 video clocks are used to create two internal clocks: one for
operating the video input interface (clk_dv1_if, clk_dv2_if), and one for operating the
main video processing pipeline (clk_dv1_proc, clk_dv2_proc).
The audio interface normally operates in slave mode (over-sampling clock, word
select and bit clock are provided from the externally connected I
2
S master). However
the PNX8510/11 can be operated in master mode. This mode only requires the
over-sampling clock to be provided. The bit clock and the word select signals are
subdivided from the over-sampling clock and provided to the chip pins.
Remark:
Both video clocks (DV_CLK1 and DV_CLK2) and an audio clock
(I2S_AOS1_CLK) have to be connected to the device for proper functioning of the I
2
C
programming interface. These clocks must be provided before the reset line
(RESET_N) is pulled high to ensure correct initialization of the device. For more
information refer to
Section 10.4
.
If the two video pipelines are sourced by only one video input interface operating in
sliced mode, both video pipelines must receive the same input clock originating from
the same sliced data source.
7.6.1
Clocks video submodule
The generation of the various clock signals needed for video pipelines takes place in
the clocks video module.
Figure 29
shows a block diagram of this module. The
configuration registers for the clocks module can be found in
Section 8.2
.
7.6.2
Clocks audio submodule
The input clocks for the audio block are generated in the clocks audio submodule.
Figure 30
shows a block diagram for this submodule
Fig 29.
Clocks video submodule
MDB657
CLOCK DIVIDER
&
DE-GILITCHER
clocks_sel
div by 1, 2, 3 or 4
CLOCK DIVIDER
&
DE-GILITCHER
clk_dv_if_out
dv_clk
sel_v
test
test
clocks_sel
div by 1, 2, 3 or 4
dv_clk
dv_clk
clk_dv_proc_out
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