
2007 Microchip Technology Inc.
Preliminary
DS41236C-page 61
PIC12F508/509/16F505
RETLW
Syntax:
Operands:
Operation:
Return with Literal in W
[
label
] RETLW k
0
≤
k
≤
255
k
→
(W);
TOS
→
PC
None
The W register is loaded with the
eight-bit literal ‘k’. The program
counter is loaded from the top of
the stack (the return address). This
is a two-cycle instruction.
Status Affected:
Description:
RLF
Syntax:
Operands:
Rotate Left f through Carry
[
label
]
0
≤
f
≤
31
d
∈
[0,1]
See description below
C
The contents of register ‘f’ are
rotated one bit to the left through
the Carry flag. If ‘d’ is ‘
0
’, the result
is placed in the W register. If ‘d’ is
‘
1
’, the result is stored back in
register ‘f’.
RLF f,d
Operation:
Status Affected:
Description:
RRF
Syntax:
Operands:
Rotate Right f through Carry
[
label
] RRF f,d
0
≤
f
≤
31
d
∈
[0,1]
See description below
C
The contents of register ‘f’ are
rotated one bit to the right through
the Carry flag. If ‘d’ is ‘
0
’, the result
is placed in the W register. If ‘d’ is
‘
1
’, the result is placed back in
register ‘f’.
Operation:
Status Affected:
Description:
C
register ‘f’
C
register ‘f’
SLEEP
Syntax:
Enter SLEEP Mode
[
label
]
SLEEP
Operands:
Operation:
None
00h
→
WDT;
0
→
WDT prescaler;
1
→
TO;
0
→
PD
TO, PD, RBWUF
Time-out Status bit (TO) is set. The
Power-down Status bit (PD) is
cleared.
RBWUF is unaffected.
The WDT and its prescaler are
cleared.
The processor is put into Sleep
mode with the oscillator stopped.
See
Section 7.9 “Power-down
Mode (Sleep)”
on Sleep for more
details.
Status Affected:
Description:
SUBWF
Syntax:
Subtract W from f
[
label
]
0
≤
f
≤
31
d
∈
[0,1]
(f) – (W)
→ (
dest)
C, DC, Z
Subtract (2’s complement method)
the W register from register ‘f’. If ‘d’
is ‘
0
’, the result is stored in the W
register. If ‘d’ is ‘
1
’, the result is
stored back in register ‘f’.
SUBWF f,d
Operands:
Operation:
Status Affected:
Description:
SWAPF
Syntax:
Operands:
Swap Nibbles in f
[
label
] SWAPF f,d
0
≤
f
≤
31
d
∈
[0,1]
(f<3:0>)
→
(dest<7:4>);
(f<7:4>)
→
(dest<3:0>)
None
The upper and lower nibbles of
register ‘f’ are exchanged. If ‘d’ is
‘
0
’, the result is placed in W
register. If ‘d’ is ‘
1
’, the result is
placed in register ‘f’.
Operation:
Status Affected:
Description: