參數(shù)資料
型號(hào)： PIC12F505
廠商： Microchip Technology Inc.
元件分類： 8位微控制器
英文描述： 8/14-Pin, 8-Bit Flash Microcontrollers
中文描述： 8/14-Pin，8位閃存微控制器
文件頁(yè)數(shù)： 28/100頁(yè)
文件大?。?/td> 741K
代理商： PIC12F505
PIC12F508/509/16F505
DS41236C-page 26
Preliminary
2007 Microchip Technology Inc.
4.9
Indirect Data Addressing: INDF
and FSR Registers
The INDF register is not a physical register.
Addressing INDF actually addresses the register
whose address is contained in the FSR register (FSR
is a
pointer
). This is indirect addressing.
4.9.1
INDIRECT ADDRESSING
Register file 07 contains the value 10h
Register file 08 contains the value 0Ah
Load the value 07 into the FSR register
A read of the INDF register will return the value
of 10h
Increment the value of the FSR register by one
(FSR = 08)
A read of the INDR register now will return the
value of 0Ah.
Reading INDF itself indirectly (FSR =
0
) will produce
00h. Writing to the INDF register indirectly results in a
no operation (although Status bits may be affected).
A simple program to clear RAM locations 10h-1Fh
using indirect addressing is shown in Example 4-1.
EXAMPLE 4-1:
HOW TO CLEAR RAM
USING INDIRECT
ADDRESSING
The FSR is a 5-bit wide register. It is used in conjunction
with the INDF register to indirectly address the data
memory area.
The FSR<4:0> bits are used to select data memory
addresses 00h to 1Fh.
FIGURE 4-7:
DIRECT/INDIRECT ADDRESSING (PIC12F508/509)
PIC12F508
– Does not use banking. FSR <7:5> are
unimplemented and read as ‘
1
’s.
PIC12F509
– Uses FSR<5>. Selects between bank 0
and bank 1. FSR<7:6> is unimplemented, read as ‘
1
’.
PIC16F505
– Uses FSR<6:5>. Selects from bank 0 to
bank 3. FSR<7> is unimplemented, read as ‘
1
’.
MOVLW
MOVWF
CLRF
0x10
FSR
INDF
;initialize pointer
;to RAM
;clear INDF
;register
;inc pointer
;all done
;NO, clear next
NEXT
INCF
BTFSC
GOTO
FSR,F
FSR,4
NEXT
CONTINUE
:
:
;YES, continue
Note 1:
For register map detail, see
Section 4.3 “Data Memory Organization”
.
PIC12F509.
2:
Bank
Location Select
Location Select
Bank Select
Indirect Addressing
Direct Addressing
Data
Memory
(1)
0Fh
10h
Bank 0
Bank 1
(2)
0
4
5
6
(FSR)
00
01
00h
1Fh
3Fh
(opcode)
0
4
5
6
(FSR)
Addresses
map back to
addresses
in Bank 0.
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