參數(shù)資料
型號(hào)： PIC12F505
廠商： Microchip Technology Inc.
元件分類： 8位微控制器
英文描述： 8/14-Pin, 8-Bit Flash Microcontrollers
中文描述： 8/14-Pin，8位閃存微控制器
文件頁(yè)數(shù)： 58/100頁(yè)
文件大?。?/td> 741K
代理商： PIC12F505
PIC12F508/509/16F505
DS41236C-page 56
Preliminary
2007 Microchip Technology Inc.
TABLE 8-2:
INSTRUCTION SET SUMMARY
Mnemonic,
Operands
Description
Cycles
12-Bit Opcode
Status
Affected
Notes
MSb
LSb
ADDWF
ANDWF
CLRF
CLRW
COMF
DECF
DECFSZ
INCF
INCFSZ
IORWF
MOVF
MOVWF
NOP
RLF
RRF
SUBWF
SWAPF
XORWF
f, d
f, d
f
—
f, d
f, d
f, d
f, d
f, d
f, d
f, d
f
—
f, d
f, d
f, d
f, d
f, d
Add W and f
AND W with f
Clear f
Clear W
Complement f
Decrement f
Decrement f, Skip if 0
Increment f
Increment f, Skip if 0
Inclusive OR W with f
Move f
Move W to f
No Operation
Rotate left f through Carry
Rotate right f through Carry
Subtract W from f
Swap f
Exclusive OR W with f
BIT-ORIENTED FILE REGISTER OPERATIONS
Bit Clear f
Bit Set f
Bit Test f, Skip if Clear
Bit Test f, Skip if Set
LITERAL AND CONTROL OPERATIONS
AND literal with W
Call Subroutine
Clear Watchdog Timer
Unconditional branch
Inclusive OR literal with W
Move literal to W
Load OPTION register
Return, place literal in W
Go into Standby mode
Load TRIS register
Exclusive OR literal to W
The 9th bit of the program counter will be forced to a ‘
0
’ by any instruction that writes to the PC except for
GOTO
. See
Section 4.7 “Program Counter”
.
When an I/O register is modified as a function of itself (e.g.
MOVF PORTB, 1
), the value used will be that
value present on the pins themselves. For example, if the data latch is ‘
1
’ for a pin configured as input and
is driven low by an external device, the data will be written back with a ‘
0
’.
The instruction
TRIS f
, where f = 6, causes the contents of the W register to be written to the tri-state
latches of PORTB. A ‘
1
’ forces the pin to a high-impedance state and disables the output buffers.
If this instruction is executed on the TMR0 register (and, where applicable, d =
1
), the prescaler will be
cleared (if assigned to TMR0).
1
1
1
1
1
1
1
(2)
1
1
(2)
1
1
1
1
1
1
1
1
1
0001
0001
0000
0000
0010
0000
0010
0010
0011
0001
0010
0000
0000
0011
0011
0000
0011
0001
11df
01df
011f
0100
01df
11df
11df
10df
11df
00df
00df
001f
0000
01df
00df
10df
10df
10df
ffff
ffff
ffff
0000
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
0000
ffff
ffff
ffff
ffff
ffff
C, DC, Z
Z
Z
Z
Z
Z
None
Z
None
Z
Z
None
None
C
C
C, DC, Z
None
Z
1, 2, 4
2, 4
4
2, 4
2, 4
2, 4
2, 4
2, 4
2, 4
1, 4
2, 4
2, 4
1, 2, 4
2, 4
2, 4
BCF
BSF
BTFSC
BTFSS
f, b
f, b
f, b
f, b
1
1
1
(2)
1
(2)
0100
0101
0110
0111
bbbf
bbbf
bbbf
bbbf
ffff
ffff
ffff
ffff
None
None
None
None
2, 4
2, 4
ANDLW
CALL
CLRWDT
GOTO
IORLW
MOVLW
OPTION
RETLW
SLEEP
TRIS
XORLW
Note 1:
k
k
—
k
k
k
—
k
—
f
k
1
2
1
2
1
1
1
2
1
1
1
1110
1001
0000
101k
1101
1100
0000
1000
0000
0000
1111
kkkk
kkkk
0000
kkkk
kkkk
kkkk
0000
kkkk
0000
0000
kkkk
kkkk
kkkk
0100
kkkk
kkkk
kkkk
0010
kkkk
0011
0fff
kkkk
Z
None
TO
,
PD
None
Z
None
None
None
TO
,
PD
None
Z
1
3
2:
3:
4:
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