參數(shù)資料
型號(hào)： PIC12F505
廠商： Microchip Technology Inc.
元件分類： 8位微控制器
英文描述： 8/14-Pin, 8-Bit Flash Microcontrollers
中文描述： 8/14-Pin，8位閃存微控制器
文件頁(yè)數(shù)： 15/100頁(yè)
文件大?。?/td> 741K
代理商： PIC12F505
2007 Microchip Technology Inc.
Preliminary
DS41236C-page 13
PIC12F508/509/16F505
TABLE 3-3:
PIC16F505 PINOUT DESCRIPTION
Name
Function
Input
Type
Output
Type
Description
RB0/ICSPDAT
RB0
TTL
CMOS Bidirectional I/O pin. Can be software programmed for internal
weak pull-up and wake-up from Sleep on pin change.
CMOS In-Circuit Serial Programming data pin.
CMOS Bidirectional I/O pin. Can be software programmed for internal
weak pull-up and wake-up from Sleep on pin change.
CMOS In-Circuit Serial Programming clock pin.
CMOS Bidirectional I/O pin.
—
Input port. Can be software programmed for internal weak
pull-up and wake-up from Sleep on pin change.
—
Master Clear (Reset). When configured as MCLR, this pin is
an active-low Reset to the device. Voltage on MCLR/V
PP
must
not exceed V
DD
during normal device operation or the device
will enter Programming mode. Weak pull-up always on if
configured as MCLR.
—
Programming voltage input.
CMOS Bidirectional I/O pin. Can be software programmed for internal
weak pull-up and wake-up from Sleep on pin change.
XTAL
Oscillator crystal output. Connections to crystal or resonator in
Crystal Oscillator mode (XT, HS and LP modes only).
CMOS In EXTRC and INTRC modes, the pin output can be
configured for CLKOUT, which has 1/4 the frequency of OSC1
and denotes the instruction cycle rate.
CMOS Bidirectional I/O pin.
—
Crystal input.
—
External clock source input.
CMOS Bidirectional I/O pin.
CMOS Bidirectional I/O pin.
CMOS Bidirectional I/O pin.
CMOS Bidirectional I/O pin.
CMOS Bidirectional I/O pin.
CMOS Bidirectional I/O pin.
—
Clock input to TMR0.
P
Positive supply for logic and I/O pins.
P
Ground reference for logic and I/O pins.
I = Input, O = Output, I/O = Input/Output, P = Power, — = Not used, TTL = TTL input,
ST = Schmitt Trigger input, HV = High Voltage
ICSPDAT
RB1
ST
TTL
RB1/ICSPCLK
ICSPCLK
RB2
RB3
ST
TTL
TTL
RB2
RB3/MCLR/V
PP
MCLR
ST
V
PP
RB4
HV
TTL
RB4/OSC2/CLKOUT
OSC2
—
CLKOUT
—
RB5/OSC1/CLKIN
RB5
OSC1
CLKIN
RC0
RC1
RC2
RC3
RC4
RC5
T0CKI
V
DD
V
SS
TTL
XTAL
ST
TTL
TTL
TTL
TTL
TTL
TTL
ST
—
—
RC0
RC1
RC2
RC3
RC4
RC5/T0CKI
V
DD
V
SS
Legend:
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