參數(shù)資料
型號(hào)： PIC12F505
廠商： Microchip Technology Inc.
元件分類： 8位微控制器
英文描述： 8/14-Pin, 8-Bit Flash Microcontrollers
中文描述： 8/14-Pin，8位閃存微控制器
文件頁(yè)數(shù)： 48/100頁(yè)
文件大?。?/td> 741K
代理商： PIC12F505
PIC12F508/509/16F505
DS41236C-page 46
Preliminary
2007 Microchip Technology Inc.
7.3.2
MCLR ENABLE
This configuration bit, when unprogrammed (left in the
‘
1
’ state), enables the external MCLR function. When
programmed, the MCLR function is tied to the internal
V
DD
and the pin is assigned to be a I/O. See Figure 7-7.
FIGURE 7-7:
MCLR SELECT
7.4
Power-on Reset (POR)
The PIC12F508/509/16F505 devices incorporate an
on-chip Power-on Reset (POR) circuitry, which
provides an internal chip Reset for most power-up
situations.
The on-chip POR circuit holds the chip in Reset until
V
DD
has reached a high enough level for proper oper-
ation. To take advantage of the internal POR, program
the (GP3/RB3)/MCLR/V
PP
pin as MCLR and tie
through a resistor to V
DD
, or program the pin as (GP3/
RB3). An internal weak pull-up resistor is implemented
using a transistor (refer to Table 10-2 for the pull-up
resistor ranges). This will eliminate external RC compo-
nents usually needed to create a Power-on Reset. A
maximum rise time for V
DD
is specified. See
Section 10.0 “Electrical Characteristics”
for details.
When the devices start normal operation (exit the
Reset condition), device operating parameters (volt-
age, frequency, temperature,...) must be met to ensure
operation. If these conditions are not met, the devices
must be held in Reset until the operating parameters
are met.
A simplified block diagram of the on-chip Power-on
Reset circuit is shown in Figure 7-8.
The Power-on Reset circuit and the Device Reset
Timer (see
Section 7.5 “Device Reset Timer (DRT)”
)
circuit are closely related. On power-up, the Reset latch
is set and the DRT is reset. The DRT timer begins
counting once it detects MCLR to be high. After the
time-out period, which is typically 18 ms, it will reset the
Reset latch and thus end the on-chip Reset signal.
A power-up example where MCLR is held low is shown
in Figure 7-9. V
DD
is allowed to rise and stabilize before
bringing MCLR high. The chip will actually come out of
Reset T
DRT
msec after MCLR goes high.
In Figure 7-10, the on-chip Power-on Reset feature is
being used (MCLR and V
DD
are tied together or the pin
is programmed to be (GP3/RB3). The V
DD
is stable
before the start-up timer times out and there is no prob-
lem in getting a proper Reset. However, Figure 7-11
depicts a problem situation where V
DD
rises too slowly.
The time between when the DRT senses that MCLR is
high and when MCLR and V
DD
actually reach their full
value, is too long. In this situation, when the start-up
timer times out, V
DD
has not reached the V
DD
(min)
value and the chip may not function correctly. For such
situations, we recommend that external RC circuits be
used to achieve longer POR delay times (Figure 7-10).
For additional information, refer to Application Notes
AN522
“Power-Up Considerations”
(DS00522) and
AN607
“Power-up Trouble Shooting”
(DS00607).
(GP3/RB3)/MCLR/V
PP
MCLRE
Internal MCLR
GPWU/RBWU
Note:
When the devices start normal operation
(exit the Reset condition), device operat-
ing parameters (voltage, frequency, tem-
perature, etc.) must be met to ensure
operation. If these conditions are not met,
the device must be held in Reset until the
operating conditions are met.
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