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參數(shù)資料
| 型號： | PIC12C67X |
| 廠商： | Microchip Technology Inc. |
| 英文描述： | 8-Pin, 8-Bit CMOS Microcontroller with A/D Converter and EEPROM Data Memory |
| 中文描述： | 8引腳，8位CMOS微控制器與A / D轉(zhuǎn)換器和EEPROM數(shù)據(jù)存儲器 |
| 文件頁數(shù)： | 65/129頁 |
| 文件大?。?/td> | 931K |
| 代理商： | PIC12C67X |
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1999 Microchip Technology Inc.
DS30561B-page 65
PIC12C67X
9.7
The Watchdog Timer is a free running, on-chip RC
oscillator, which does not require any external compo-
nents. This RC oscillator is separate from the RC oscil-
lator of the OSC1/CLKIN pin. That means that the WDT
will run, even if the clock on the OSC1/CLKIN and
OSC2/CLKOUT pins of the device has been stopped,
for example, by execution of a
SLEEP
instruction. Dur-
ing normal operation, a WDT time-out generates a
device RESET (Watchdog Timer Reset). If the device is
in SLEEP mode, a WDT time-out causes the device to
wake-up and continue with normal operation (Watch-
dog Timer Wake-up). The WDT can be permanently
disabled
by
clearing
configuration
(Section 9.1).
Watchdog Timer (WDT)
bit
WDTE
9.7.1
WDT PERIOD
The WDT has a nominal time-out period of 18 ms (with
no prescaler). The time-out periods vary with tempera-
ture, V
DD
and process variations from part to part (see
DC specs). If longer time-out periods are desired, a
prescaler with a division ratio of up to 1:128 can be
assigned to the WDT under software control by writing
to the OPTION register. Thus, time-out periods up to
2.3 seconds can be realized.
The
CLRWDT
and
SLEEP
instructions clear the WDT
and the postscaler, if assigned to the WDT, and prevent
it from timing out early and generating a premature
device RESET condition.
The TO bit in the STATUS register will be cleared upon
a Watchdog Timer time-out.
9.7.2
WDT PROGRAMMING CONSIDERATIONS
It should also be taken into account that under worst
case conditions (V
DD
= Min., Temperature = Max., and
max. WDT prescaler), it may take several seconds
before a WDT time-out occurs.
See Example 7-1 and Example 7-2 for changing pres-
caler between WDT and Timer0.
Note:
When the prescaler is assigned to the
WDT, always execute a
CLRWDT
instruction
before changing the prescale value, other-
wise a WDT reset may occur.
FIGURE 9-15: WATCHDOG TIMER BLOCK DIAGRAM
TABLE 9-8:
Address
SUMMARY OF WATCHDOG TIMER REGISTERS
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
2007h
Config. bits
(1)
OPTION
MCLRE
CP1
CP0
PWRTE
WDTE
FOSC2
FOSC1
FOSC0
81h
GPPU
INTEDG
T0CS
T0SE
PSA
PS2
PS1
PS0
Legend:
Note 1:
Shaded cells are not used by the Watchdog Timer.
See Register 9-1 for operation of these bits. Not all CP0 and CP1 bits are shown.
From TMR0 Clock Source
(Figure 7-5)
To TMR0 (Figure 7-5)
Postscaler
WDT Timer
WDT
Enable Bit
0
1
M
U
X
PSA
8 - to - 1 MUX
PS<2:0>
0
1
MUX
PSA
WDT
Time-out
Note:
PSA and PS<2:0> are bits in the OPTION register.
8
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