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參數(shù)資料
| 型號： | PIC12C67X |
| 廠商： | Microchip Technology Inc. |
| 英文描述： | 8-Pin, 8-Bit CMOS Microcontroller with A/D Converter and EEPROM Data Memory |
| 中文描述： | 8引腳，8位CMOS微控制器與A / D轉(zhuǎn)換器和EEPROM數(shù)據(jù)存儲(chǔ)器 |
| 文件頁數(shù)： | 15/129頁 |
| 文件大?。?/td> | 931K |
| 代理商： | PIC12C67X |
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1999 Microchip Technology Inc.
DS30561B-page 15
PIC12C67X
4.2.2.1
STATUS REGISTER
The STATUS Register, shown in Register 4-1, contains
the arithmetic status of the ALU, the RESET status and
the bank select bits for data memory.
The STATUS Register can be the destination for any
instruction, as with any other register. If the STATUS
Register is the destination for an instruction that affects
the Z, DC or C bits, then the write to these three bits is
disabled. These bits are set or cleared according to the
device logic. Furthermore, the TO and PD bits are not
writable. Therefore, the result of an instruction with the
STATUS Register as destination may be different than
intended.
For example,
CLRF STATUS
will clear the upper three
bits and set the Z bit. This leaves the STATUS Register
as
000u u1uu
(where
u
= unchanged).
It is recommended, therefore, that only
BCF, BSF,
SWAPF
and
MOVWF
instructions are used to alter the
STATUS Register, because these instructions do not
affect the Z, C or DC bits from the STATUS Register.
For other instructions, not affecting any status bits, see
the "Instruction Set Summary."
Note 1:
Bits IRP and RP1 (STATUS<7:6>) are not
used by the PIC12C67X and should be
maintained clear. Use of these bits as
general purpose R/W bits is NOT recom-
mended, since this may affect upward
compatibility with future products.
2:
The C and DC bits operate as a borrow
and digit borrow bit, respectively, in sub-
traction. See the
SUBLW
and
SUBWF
instructions for examples.
REGISTER 4-1:
STATUS REGISTER (ADDRESS 03h, 83h)
Reserved Reserved
IRP
bit7
R/W-0
RP0
R-1
TO
R-1
PD
R/W-x
Z
R/W-x
DC
R/W-x
C
RP1
R = Readable bit
W = Writable bit
U = Unimplemented bit,
r
ead as ‘0’
- n = Value at POR reset
bit0
bit 7:
IRP:
Register Bank Select bit (used for indirect addressing)
1
= Bank 2, 3 (100h - 1FFh)
0
= Bank 0, 1 (00h - FFh)
The IRP bit is reserved; always maintain this bit clear.
RP<1:0>:
Register Bank Select bits (used for direct addressing)
11
= Bank 3 (180h - 1FFh)
10
= Bank 2 (100h - 17Fh)
01
= Bank 1 (80h - FFh)
00
= Bank 0 (00h - 7Fh)
Each bank is 128 bytes. The RP1 bit is reserved; always maintain this bit clear.
TO:
Time-out bit
1
= After power-up,
CLRWDT
instruction, or
SLEEP
instruction
0
= A WDT time-out occurred
PD:
Power-down bit
1
= After power-up or by the
CLRWDT
instruction
0
= By execution of the
SLEEP
instruction
Z:
Zero bit
1
= The result of an arithmetic or logic operation is zero
0
= The result of an arithmetic or logic operation is not zero
DC:
Digit Carry/borrow bit (
ADDWF
,
ADDLW,SUBLW,SUBWF
instructions) (for borrow the polarity is reversed)
1
= A carry-out from the 4th low order bit of the result occurred
0
= No carry-out from the 4th low order bit of the result
C:
Carry/borrow bit (
ADDWF
,
ADDLW,SUBLW,SUBWF
instructions)
1
= A carry-out from the most significant bit of the result occurred
0
= No carry-out from the most significant bit of the result occurred
bit 6-5:
bit 4:
bit 3:
bit 2:
bit 1:
bit 0:
Note:
For borrow
the polarity is reversed. A subtraction is executed by adding the two’s complement of the sec-
ond operand. For rotate (
RRF
,
RLF
) instructions, this bit is loaded with either the high or low order bit of
the source register.
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