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| 型號(hào)： | PIC12C67X |
| 廠商： | Microchip Technology Inc. |
| 英文描述： | 8-Pin, 8-Bit CMOS Microcontroller with A/D Converter and EEPROM Data Memory |
| 中文描述： | 8引腳，8位CMOS微控制器與A / D轉(zhuǎn)換器和EEPROM數(shù)據(jù)存儲(chǔ)器 |
| 文件頁(yè)數(shù)： | 64/129頁(yè) |
| 文件大?。?/td> | 931K |
| 代理商： | PIC12C67X |
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PIC12C67X
DS30561B-page 64
1999 Microchip Technology Inc.
9.5.1
TMR0 INTERRUPT
An overflow (FFh
→
00h) in the TMR0 register will set
flag bit T0IF (INTCON<2>). The interrupt can be
enabled/disabled by setting/clearing enable bit T0IE
(INTCON<5>) (Section 7.0). The flag bit T0IF
(INTCON<2>) will be set, regardless of the state of the
enable bits. If used, this flag must be cleared in software.
9.5.2
INT INTERRUPT
External interrupt on GP2/INT pin is edge triggered;
either rising if bit INTEDG (OPTION<6>) is set, or fall-
ing, if the INTEDG bit is clear. When a valid edge
appears on the GP2/INT pin, flag bit INTF
(INTCON<1>) is set. This interrupt can be disabled by
clearing enable bit INTE (INTCON<4>). Flag bit INTF
must be cleared in software in the interrupt service rou-
tine before re-enabling this interrupt. The INT interrupt
can wake-up the processor from SLEEP, if bit INTE was
set prior to going into SLEEP. The status of global inter-
rupt enable bit GIE decides whether or not the proces-
sor branches to the interrupt vector following wake-up.
See Section 9.8 for details on SLEEP mode.
9.5.3
GPIO INTCON CHANGE
An input change on GP3, GP1 or GP0 sets flag bit GPIF
(INTCON<0>). The interrupt can be enabled/disabled by
setting/clearing
enable
bit
(Section 5.1) . This flag bit GPIF (INTCON<0>) will be
set, regardless of the state of the enable bits. If used, this
flag must be cleared in software.
GPIE
(INTCON<3>)
9.6
During an interrupt, only the return PC value is saved
on the stack. Typically, users may wish to save key reg-
isters during an interrupt (i.e., W register and STATUS
register). This will have to be implemented in software.
Example 9-1 shows the storing and restoring of the
STATUS and W registers. The register, W_TEMP, must
be defined in both banks and must be defined at the
same offset from the bank base address (i.e., if
W_TEMP is defined at 0x20 in bank 0, it must also be
defined at 0xA0 in bank 1).
Example 9-2 shows the saving and restoring of STA-
TUS and W using RAM locations 0x70 - 0x7F.
W_TEMP is defined at 0x70 and STATUS_TEMP is
defined at 0x71.
The example:
a)
Stores the W register.
b)
Stores the STATUS register in bank 0.
c)
Executes the ISR code.
d)
Restores the STATUS register (and bank select
bit).
e)
Restores the W register.
f)
Returns from interrupt.
Context Saving During Interrupts
EXAMPLE 9-1:
SAVING STATUS AND W REGISTERS USING GENERAL PURPOSE RAM
(0x20 - 0x6F)
MOVWF W_TEMP ;Copy W to TEMP register, could be bank one or zero
SWAPF STATUS,W ;Swap status to be saved into W
BCF STATUS,RP0 ;Change to bank zero, regardless of current bank
MOVWF STATUS_TEMP ;Save status to bank zero STATUS_TEMP register
:
:(ISR)
:
SWAPF STATUS_TEMP,W ;Swap STATUS_TEMP register into W
;(sets bank to original state)
MOVWF STATUS ;Move W into STATUS register
SWAPF W_TEMP,F ;Swap W_TEMP
SWAPF W_TEMP,W ;Swap W_TEMP into W
RETFIE ;Return from interrupt
EXAMPLE 9-2:
SAVING STATUS AND W REGISTERS USING SHARED RAM (0x70 - 0x7F)
MOVWF W_TEMP ;Copy W to TEMP register (bank independent)
MOVF STATUS,W ;Move STATUS register into W
MOVWF STATUS_TEMP ;Save contents of STATUS register
:
:(ISR)
:
MOVF STATUS_TEMP,W ;Retrieve copy of STATUS register
MOVWF STATUS ;Restore pre-isr STATUS register contents
SWAPF W_TEMP,F ;
SWAPF W_TEMP,W ;Restore pre-isr W register contents
RETFIE ;Return from interrupt
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