TM Family Datasheet Page 70 of 77 July 2009 – Rev" />
參數(shù)資料
型號(hào)： PI7C9X20404SLCFDE
廠商： Pericom
文件頁數(shù)： 68/77頁
文件大?。?/td> 0K
描述： IC PCIE PACKET SWITCH 128LQFP
標(biāo)準(zhǔn)包裝： 90
系列： SlimLine™
應(yīng)用： 封裝開關(guān)，4 端口/4 線道
接口： PCI Express
封裝/外殼： 128-LQFP 裸露焊盤
供應(yīng)商設(shè)備封裝： 128-LQFP（14x14）
包裝： 托盤
安裝類型： 表面貼裝
PI7C9X20404SL
4Port-4Lane PCI Express Switch
SlimLine
TM Family
Datasheet
Page 70 of 77
July 2009 – Revision 1.2
Pericom Semiconductor
9.4
BOUNDARY SCAN REGISTER
The boundary scan register has a set of serial shift-register cells. A chain of boundary scan cells is formed by
connected the internal signal of the PI7C9X20404SL package pins. The VDD, VSS, and JTAG pins are not
in the boundary scan chain. The input to the shift register is TDI and the output from the shift register is
TDO. There are 4 different types of boundary scan cells, based on the function of each signal pin.
The boundary scan register cells are dedicated logic and do not have any system function. Data may be
loaded into the boundary scan register master cells from the device input pins and output pin-drivers in
parallel by the mandatory SAMPLE and EXTEST instructions. Parallel loading takes place on the rising
edge of TCK.
9.5
JTAG BOUNDARY SCAN REGISTER ORDER
Table 9-3 JTAG boundary scan register definition
Boundary Scan
Register Number
Pin Name
Pin No
Type
Tri-state Control Cell
0
WAKEUP _L
6
Input
4
1
SLOT_IMP[2]
7
Bidir
4
2
NC
9
Bidir
4
3
TEST5
10
Bidir
4
Control
5
TEST4
11
Bidir
4
6
TEST3
12
Bidir
4
7
SMBCLK
13
Bidir
4
8
SMBDATA
16
Bidir
4
9
PWR_SAV
17
Bidir
4
10
DEQ[3]
18
Bidir
4
11
GPIO[0]
21
Bidir
12
Control
13
GPIO[1]
22
Bidir
14
Control
15
GPIO[2]
23
Bidir
16
Control
17
GPIO[3]
24
Bidir
18
Control
19
GPIO[4]
25
Bidir
20
Control
21
GPIO[5]
26
Bidir
22
Control
23
GPIO[6]
27
Bidir
24
Control
25
GPIO[7]
28
Bidir
26
Control
27
TEST1
31
Bidir
4
28
HIDRV
32
Bidir
4
29
LOWDRV
33
Bidir
4
30
DTX[3]
38
Bidir
4
31
EECLK
40
Output2
32
EEPD
41
Bidir
33
Control
34
PERST_L
43
Input
35
PWR_IND[1]
Output2
36
PWR_IND[3]
Output2
37
PORTERR[0]
45
Output2
38
ATT_IND[1]
Output2
39
ATT_IND[3]
Output2
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