參數資料
| 型號： | PI7C9X20404SLCFDE |
| 廠商： | Pericom |
| 文件頁數： | 19/77頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC PCIE PACKET SWITCH 128LQFP |
| 標準包裝： | 90 |
| 系列： | SlimLine™ |
| 應用： | 封裝開關，4 端口/4 線道 |
| 接口： | PCI Express |
| 封裝/外殼： | 128-LQFP 裸露焊盤 |
| 供應商設備封裝： | 128-LQFP（14x14） |
| 包裝： | 托盤 |
| 安裝類型： | 表面貼裝 |
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PI7C9X20404SL
4Port-4Lane PCI Express Switch
SlimLine
TM Family
Datasheet
Page 26 of 77
July 2009 – Revision 1.2
Pericom Semiconductor
ADDRESS
PCI CFG OFFSET
DESCRIPTION
F0h (Port 0)
F0h: Bit [28]
80h (Port 0)
80h: Bit[21]
ECh (Port 0)
ECh: Bit [25:24]
84h (Port 0)
84h: Bit [14:13]
Slot Clock Configuration for Port 0
Bit [1]: When set, the component uses the clock provided on the
connector
Device specific Initialization for Port 0
Bit [2]: When set, the DSI is required
Port Number for Port 0
Bit [5:4]: It represents the logic port numbering for physical port
0
PMCSR Data Scale for Port 0
Bit [7:6]: It represents the PMCSR Data Scale for physical port 0
20h
154h (Port 0)
154h: Bit [7:1]
VC0 TC/VC Map for Port 0
Bit [15:9]: When set, it indicates the corresponding TC is
mapped into VC0
E0h (Port1)
E0h: Bit [24]
F0h (Port 1)
F0h: Bit [28]
80h (Port 1)
80h: Bit[21]
ECh (Port 1)
ECh: Bit [25:24]
84h (Port 1)
84h: Bit [14:13]
PCIe Capability Slot Implemented for Port 1
Bit [0]: When set, the slot is implemented for Port 1
Slot Clock Configuration for Port 1
Bit [1]: When set, the component uses the clock provided on the
Connector
Device specific Initialization for Port 1
Bit [2]: When set, the DSI is required
Port Number for Port 1
Bit [5:4]: It represents the logic port numbering for physical port
1
PMCSR Data Scale for Port 1
Bit [7:6]: It represents the PMCSR Data Scale for physical port 1
22h
154h (Port 1)
154h: Bit [7:1]
VC0 TC/VC Map for Port 1
Bit [15:9]: When set, it indicates the corresponding TC is
mapped into VC0
E0h (Port 2)
E0h: Bit [24]
F0h (Port 2)
F0h: Bit [28]
80h (Port 2)
80h: Bit[21]
ECh (Port 2)
ECh: Bit [25:24]
84h (Port 2)
84h: Bit [14:13]
PCIe Capability Slot Implemented for Port 2
Bit [0]: When set, the slot is implemented for Port 2
Slot Clock Configuration for Port 2
Bit [1]: When set, the component uses the clock provided on the
Connector
Device specific Initialization for Port 2
Bit [2]: When set, the DSI is required
Port Number for Port 2
Bit [5:4]: It represents the logic port numbering for physical port
2
PMCSR Data Scale for Port 2
Bit [7:6]: It represents the PMCSR Data Scale for physical port 2
24h
154h (Port 2)
154h: Bit [7:1]
VC0 TC/VC Map for Port 2
Bit [15:9]: When set, it indicates the corresponding TC is
mapped into VC0
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相關代理商/技術參數 |
參數描述 |
|---|---|
| PI7C9X20404SLCFDEX | 功能描述:外圍驅動器與原件 - PCI 4port 4lane PCIe Packet Switch RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| PI7C9X20505GPBNDE | 功能描述:外圍驅動器與原件 - PCI 5port 5lane PCIe PacketSwitch RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| PI7C9X20508GPANDE | 制造商:Pericom Semiconductor Corporation 功能描述:5-PORT, 8-LANE, GREENPACKET- PCIE PACKET SWITCH - Rail/Tube |
| PI7C9X20508GPBEVB | 制造商:Pericom Semiconductor Corporation 功能描述:EVAL BOARD - Boxed Product (Development Kits) |
| PI7C9X20508GPBNDE | 功能描述:外圍驅動器與原件 - PCI 5port 8lane PCIe PacketSwitch RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
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