TM Family Datasheet Page 41 of 77 July 2009 – Rev" />
參數(shù)資料
型號(hào): PI7C9X20404SLCFDE
廠商: Pericom
文件頁(yè)數(shù): 36/77頁(yè)
文件大小: 0K
描述: IC PCIE PACKET SWITCH 128LQFP
標(biāo)準(zhǔn)包裝: 90
系列: SlimLine™
應(yīng)用: 封裝開關(guān),4 端口/4 線道
接口: PCI Express
封裝/外殼: 128-LQFP 裸露焊盤
供應(yīng)商設(shè)備封裝: 128-LQFP(14x14)
包裝: 托盤
安裝類型: 表面貼裝
PI7C9X20404SL
4Port-4Lane PCI Express Switch
SlimLine
TM Family
Datasheet
Page 41 of 77
July 2009 – Revision 1.2
Pericom Semiconductor
BIT
FUNCTION
TYPE
DESCRIPTION
00b: D0 state
01b: D1 state
10b: D2 state
11b: D3 hot state
Reset to 00b.
2
Reserved
RO
Reset to 0b.
3
No_Soft_Reset
RO
When set, this bit indicates that device transitioning from D3hot to D0 does
not perform an internal reset. When clear, an internal reset is performed when
power state transits from D3hot to D0. This bit can be rewritten with
EEPROM programming. The default value may be changed by SMBus or
auto-loading from EEPROM.
Reset to 1b.
7:4
Reserved
RO
Reset to 0b.
8
PME# Enable
RWS
When asserted, the Switch will generate the PME# message. Reset to 0b.
12:9
Data Select
RW
Select data registers.
Reset to 0h.
14:13
Data Scale
RO
Reset to 00b.
15
PME status
ROS
Read as 0b as the PME# message is not implemented.
7.2.33
PPB SUPPORT EXTENSIONS – OFFSET 84h
BIT
FUNCTION
TYPE
DESCRIPTION
21:16
Reserved
RO
Reset to 000000b.
22
B2_B3 Support for
D3HOT
RO
Does not apply to PCI Express. Must be hardwired to 0b.
23
Bus Power / Clock
Control Enable
RO
Does not apply to PCI Express. Must be hardwired to 0b.
7.2.34
DATA REGISTER – OFFSET 84h
BIT
FUNCTION
TYPE
DESCRIPTION
31:24
Data Register
RO
Data Register. The default value may be changed by SMBus or auto-loading
from EEPROM.
Reset to 0b.
7.2.35
MSI CAPABILITY ID REGISTER – OFFSET 8Ch (Downstream Port Only)
BIT
FUNCTION
TYPE
DESCRIPTION
7:0
Enhanced
Capabilities ID
RO
Read as 05h to indicate that this is message signal interrupt capability
register.
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