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參數(shù)資料
| 型號： | PI7C9X20404SLCFDE |
| 廠商： | Pericom |
| 文件頁數(shù)： | 20/77頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC PCIE PACKET SWITCH 128LQFP |
| 標(biāo)準(zhǔn)包裝： | 90 |
| 系列： | SlimLine™ |
| 應(yīng)用： | 封裝開關(guān)，4 端口/4 線道 |
| 接口： | PCI Express |
| 封裝/外殼： | 128-LQFP 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 128-LQFP（14x14） |
| 包裝： | 托盤 |
| 安裝類型： | 表面貼裝 |
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PI7C9X20404SL
4Port-4Lane PCI Express Switch
SlimLine
TM Family
Datasheet
Page 27 of 77
July 2009 – Revision 1.2
Pericom Semiconductor
ADDRESS
PCI CFG OFFSET
DESCRIPTION
E0h (Port 3)
E0h: Bit [24]
F0h (Port 3)
F0h: Bit [28]
80h (Port 3)
80h: Bit[21]
ECh (Port 3)
ECh: Bit [25:24]
84h (Port 3)
84h: Bit [14:13]
PCIe Capability Slot Implemented for Port 3
Bit [0]: When set, the slot is implemented for Port 3
Slot Clock Configuration for Port 3
Bit [1]: When set, the component uses the clock provided on the
Connector
Device specific Initialization for Port 3
Bit [2]: When set, the DSI is required
Port Number for Port 3
Bit [5:4]: It represents the logic port numbering for physical port
3
PMCSR Data Scale for Port 3
Bit [7:6]: It represents the PMCSR Data Scale for physical port 3
26h
154h (Port 3)
154h: Bit [7:1]
VC0 TC/VC Map for Port 3
Bit [15:9]: When set, it indicates the corresponding TC is
mapped into VC0
32h
F4h (Port 1)
F4h: Bit [15:0]
Slot Capability 0 of Port 1
Bit [15:0]: Mapping to the low word of slot capability register
34h
F4h (Port 2)
F4h: Bit [15:0]
Slot Capability 0 of Port 2
Bit [15:0]: Mapping to the low word of slot capability register
36h
F4h (Port 3)
F4h: Bit [15:0]
Slot Capability 0 of Port 3
Bit [15:0]: Mapping to the low word of slot capability register
42h
F4h (Port 1)
F4h: Bit [31:16]
Slot Capability 1 of Port 1
Bit [15:0]: Mapping to the high word of slot capability register
44h
F4h (Port 2)
F4h: Bit [31:16]
Slot Capability 1 of Port 2
Bit [15:0]: Mapping to the high word of slot capability register
46h
F4h (Port 3)
F4h: Bit [31:16]
Slot Capability 1 of Port 3
Bit [15:0]: Mapping to the high word of slot capability register
50h
84h (Port 0)
84h: Bit [3]
80h (Port 0)
80h: Bit [24:22]
80h: Bit [25]
80h: Bit [26]
80h: Bit [29:28]
No_Soft_Reset for Port 0
Bit [0]: No_Soft_Reset.
Power Management Capability for Port 0
Bit [3:1]: AUX Current.
Bit [4]: read only as 1 to indicate Bridge supports the D1 power
management state
Bit [5]: read only as 1 to indicate Bridge supports the D2 power
management state
Bit [7:6]: PME Support for D2 and D1 states
51h
84h (Port 0)
84h: Bit [31:24]
Power Management Data for Port 0
Bit [15:8]: read only as Data register
52h
84h (Port 1)
84h: Bit [3]
80h (Port 1)
80h: Bit [24:22]
80h: Bit [25]
80h: Bit [26]
80h: Bit [29:28]
No_Soft_Reset for Port 1
Bit [0]: No_Soft_Reset.
Power Management Capability for Port 1
Bit [3:1]: AUX Current.
Bit [4]: read only as 1 to indicate Bridge supports the D1 power
management state
Bit [5]: read only as 1 to indicate Bridge supports the D2 power
management state
Bit [7:6]: PME Support for D2 and D1 states
53h
84h (Port 1)
84h: Bit [31:24]
Power Management Data for Port 1
Bit [15:8]: read only as Data register
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PI7C9X20404SLCFDEX | 功能描述:外圍驅(qū)動器與原件 - PCI 4port 4lane PCIe Packet Switch RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| PI7C9X20505GPBNDE | 功能描述:外圍驅(qū)動器與原件 - PCI 5port 5lane PCIe PacketSwitch RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| PI7C9X20508GPANDE | 制造商:Pericom Semiconductor Corporation 功能描述:5-PORT, 8-LANE, GREENPACKET- PCIE PACKET SWITCH - Rail/Tube |
| PI7C9X20508GPBEVB | 制造商:Pericom Semiconductor Corporation 功能描述:EVAL BOARD - Boxed Product (Development Kits) |
| PI7C9X20508GPBNDE | 功能描述:外圍驅(qū)動器與原件 - PCI 5port 8lane PCIe PacketSwitch RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
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