TM Family Datasheet Page 43 of 77 July 2009 – Rev" />
參數(shù)資料
型號: PI7C9X20404SLCFDE
廠商: Pericom
文件頁數(shù): 38/77頁
文件大?。?/td> 0K
描述: IC PCIE PACKET SWITCH 128LQFP
標(biāo)準(zhǔn)包裝: 90
系列: SlimLine™
應(yīng)用: 封裝開關(guān),4 端口/4 線道
接口: PCI Express
封裝/外殼: 128-LQFP 裸露焊盤
供應(yīng)商設(shè)備封裝: 128-LQFP(14x14)
包裝: 托盤
安裝類型: 表面貼裝
PI7C9X20404SL
4Port-4Lane PCI Express Switch
SlimLine
TM Family
Datasheet
Page 43 of 77
July 2009 – Revision 1.2
Pericom Semiconductor
BIT
FUNCTION
TYPE
DESCRIPTION
7:0
Enhanced
Capabilities ID
RO
Read as 03h to indicate that these are VPD enhanced capability registers.
Reset to 03h.
7.2.42
NEXT ITEM POINTER REGISTER – OFFSET 9Ch (Upstream Port Only)
BIT
FUNCTION
TYPE
DESCRIPTION
15:8
Next Item Pointer
RO
Pointer points to the Vendor specific capability register (A4h).
Reset to A4h.
7.2.43
VPD REGISTER – OFFSET 9Ch (Upstream Port Only)
BIT
FUNCTION
TYPE
DESCRIPTION
17:16
Reserved
RO
Reset to 00b.
23:18
VPD Address
RW
Contains DWORD address that is used to generate read or write cycle to the
VPD table stored in EEPROM.
Reset to 000000b.
30:24
Reserved
RO
Reset to 0000000b.
31
VPD operation
RW
0b: Performs VPD read command to VPD table at the location as specified
in VPD address. This bit is kept ‘0’ and then set to ‘1’ automatically
after EEPROM cycle is finished
1b: Performs VPD write command to VPD table at the location as specified
in VPD address. This bit is kept ‘1’ and then set to ‘0’ automatically
after EEPROM cycle is finished.
Reset to 0b.
7.2.44
VPD DATA REGISTER – OFFSET A0h (Upstream Port Only)
BIT
FUNCTION
TYPE
DESCRIPTION
31:0
VPD Data
RW
When read, it returns the last data read from VPD table at the location as
specified in VPD Address.
When written, it places the current data into VPD table at the location as
specified in VPD Address.
7.2.45
VENDOR SPECIFIC CAPABILITY ID REGISTER – OFFSET A4h
BIT
FUNCTION
TYPE
DESCRIPTION
7:0
Enhanced
Capabilities ID
RO
Read as 09h to indicate that these are vendor specific capability registers.
Reset to 09h.
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