TM Family Datasheet Page 37 of 77 July 2009 – Rev" />
參數(shù)資料
型號(hào)： PI7C9X20404SLCFDE
廠商： Pericom
文件頁數(shù)： 31/77頁
文件大小： 0K
描述： IC PCIE PACKET SWITCH 128LQFP
標(biāo)準(zhǔn)包裝： 90
系列： SlimLine™
應(yīng)用： 封裝開關(guān)，4 端口/4 線道
接口： PCI Express
封裝/外殼： 128-LQFP 裸露焊盤
供應(yīng)商設(shè)備封裝： 128-LQFP（14x14）
包裝： 托盤
安裝類型： 表面貼裝
PI7C9X20404SL
4Port-4Lane PCI Express Switch
SlimLine
TM Family
Datasheet
Page 37 of 77
July 2009 – Revision 1.2
Pericom Semiconductor
BIT
FUNCTION
TYPE
DESCRIPTION
29
Received Master
Abort
RO
Set to 1 (by a requestor) whenever receiving a Completion with Unsupported
Request Completion Status in secondary side.
Reset to 0b.
30
Received System
Error
RWC
Set to 1 when the Switch sends an ERR_FATAL or ERR_NONFATAL
Message, and the SERR Enable bit in the Bridge Control register is 1.
Reset to 0b.
31
Detected Parity Error
RWC
Set to 1 whenever the secondary side of the port in a Switch receives a
Poisoned TLP.
Reset to 0b.
7.2.17
MEMORY BASE ADDRESS REGISTER – OFFSET 20h
BIT
FUNCTION
TYPE
DESCRIPTION
3:0
Reserved
RO
Reset to 0h.
15:4
Memory Base
Address [15:4]
RW
Defines the bottom address of an address range for the Bridge to determine
when to forward memory transactions from one interface to the other. The
upper 12 bits correspond to address bits [31:20] and are able to be written to.
The lower 20 bits corresponding to address bits [19:0] are assumed to be 0.
Reset to 000h.
7.2.18
MEMORY LIMIT ADDRESS REGISTER – OFFSET 20h
BIT
FUNCTION
TYPE
DESCRIPTION
19:16
Reserved
RO
Reset to 0h.
31:20
Memory Limit
Address [31:20]
RW
Defines the top address of an address range for the Bridge to determine when
to forward memory transactions from one interface to the other. The upper
12 bits correspond to address bits [31:20] and are writable. The lower 20 bits
corresponding to address bits [19:0] are assumed to be FFFFFh.
Reset to 000h.
7.2.19
PREFETCHABLE MEMORY BASE ADDRESS REGISTER – OFFSET 24h
BIT
FUNCTION
TYPE
DESCRIPTION
3:0
64-bit addressing
RO
Read as 0001b to indicate 64-bit addressing.
15:4
Prefetchable Memory
Base Address [31:20]
RW
Defines the bottom address of an address range for the Bridge to determine
when to forward memory read and write transactions from one interface to the
other. The upper 12 bits correspond to address bits [31:20] and are writable.
The lower 20 bits are assumed to be 0. The memory base register upper 32
bits contain the upper half of the base address.
Reset to 000h.
7.2.20
PREFETCHABLE MEMORY LIMIT ADDRESS REGISTER – OFFSET 24h
BIT
FUNCTION
TYPE
DESCRIPTION
19:16
64-bit addressing
RO
Read as 0001b to indicate 64-bit addressing.
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PI7C9X20404SLCFDEX 功能描述:外圍驅(qū)動(dòng)器與原件 - PCI 4port 4lane PCIe Packet Switch RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray
PI7C9X20505GPBNDE 功能描述:外圍驅(qū)動(dòng)器與原件 - PCI 5port 5lane PCIe PacketSwitch RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray
PI7C9X20508GPANDE 制造商:Pericom Semiconductor Corporation 功能描述:5-PORT, 8-LANE, GREENPACKET- PCIE PACKET SWITCH - Rail/Tube
PI7C9X20508GPBEVB 制造商:Pericom Semiconductor Corporation 功能描述:EVAL BOARD - Boxed Product (Development Kits)
PI7C9X20508GPBNDE 功能描述:外圍驅(qū)動(dòng)器與原件 - PCI 5port 8lane PCIe PacketSwitch RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray
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