TM Family Datasheet Page 61 of 79 June 2009 – " />
參數(shù)資料
型號(hào)： PI7C9X20404GPBNBE
廠商： Pericom
文件頁數(shù)： 58/79頁
文件大小： 0K
描述： IC PCIE PACKET SWITCH 148LFBGA
產(chǎn)品變化通告： Product Discontinuation Notice 22/Jan/2010
標(biāo)準(zhǔn)包裝： 189
系列： GreenPacket™
應(yīng)用： 封裝開關(guān)，4 端口/4 線道
接口： PCI Express
封裝/外殼： 148-LFBGA
供應(yīng)商設(shè)備封裝： 148-LFBGA（12x12）
包裝： 托盤
安裝類型： 表面貼裝
PI7C9X20404GP
4Port-4Lane PCI Express Switch
GreenPacket
TM Family
Datasheet
Page 61 of 79
June 2009 – Revision 1.6
Pericom Semiconductor
7.2.86
NEXT ITEM POINTER REGISTER – OFFSET 140h
BIT
FUNCTION
TYPE
DESCRIPTION
31:20
Next Capability
Offset
RO
Pointer points to the PCI Express Power Budgeting Capability register
(20Ch).
Reset to 20Ch.
7.2.87
PORT VC CAPABILITY REGISTER 1 – OFFSET 144h
BIT
FUNCTION
TYPE
DESCRIPTION
2:0
Extended VC Count
HwInt
It indicates the number of extended Virtual Channels in addition to the default
VC supported by the Switch. The default value may be changed by the status
of strapped pin or auto-loading from EEPROM.
Reset to 001b.
3
Reserved
RO
Reset to 0b.
6:4
Low Priority
Extended VC Count
RO
It indicates the number of extended Virtual Channels in addition to the default
VC belonging to the low-priority VC (LPVC) group. The default value may
be changed by SMBus or auto-loading from EEPROM.
Reset to 000b.
7
Reserved
RO
Reset to 0b.
9:8
Reference Clock
RO
It indicates the reference clock for Virtual Channels that support time-based
WRR Port Arbitration. Defined encoding is 00b for 100 ns reference clock.
Reset to 00b.
11:10
Port Arbitration
Table Entry Size
RO
Read as 10b to indicate the size of Port Arbitration table entry in the device is
4 bits.
Reset to 10b.
31:12
Reserved
RO
Reset to 0.
7.2.88
PORT VC CAPABILITY REGISTER 2 – OFFSET 148h
BIT
FUNCTION
TYPE
DESCRIPTION
7:0
VC Arbitration
Capability
RO
It indicates the types of VC Arbitration supported by the device for the LPVC
group. This field is valid when LPVC is greater than 0. The Switch supports
Hardware fixed arbitration scheme, e.g., Round Robin and Weight Round
Robin arbitration with 32 phases in LPVC.
Reset to 00000011b.
23:8
Reserved
RO
Reset to 0.
31:24
VC Arbitration Table
Offset
RO
It indicates the location of the VC Arbitration Table as an offset from the base
address of the Virtual Channel Capability register in the unit of DQWD (16
bytes).
Reset to 03h.
7.2.89
PORT VC CONTROL REGISTER – OFFSET 14Ch
BIT
FUNCTION
TYPE
DESCRIPTION
0
Load VC Arbitration
Table
RW
When set, the programmed VC Arbitration Table is applied to the hardware.
This bit always returns 0b when read.
Reset to 0b.
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