TM Family Datasheet Page 60 of 79 June 2009 – " />
參數(shù)資料
型號: PI7C9X20404GPBNBE
廠商: Pericom
文件頁數(shù): 57/79頁
文件大?。?/td> 0K
描述: IC PCIE PACKET SWITCH 148LFBGA
產(chǎn)品變化通告: Product Discontinuation Notice 22/Jan/2010
標準包裝: 189
系列: GreenPacket™
應用: 封裝開關,4 端口/4 線道
接口: PCI Express
封裝/外殼: 148-LFBGA
供應商設備封裝: 148-LFBGA(12x12)
包裝: 托盤
安裝類型: 表面貼裝
PI7C9X20404GP
4Port-4Lane PCI Express Switch
GreenPacket
TM Family
Datasheet
Page 60 of 79
June 2009 – Revision 1.6
Pericom Semiconductor
BIT
FUNCTION
TYPE
DESCRIPTION
13
Advisory Non-Fatal
Error Mask
RWS
When set, the Advisory Non-Fatal Error event is not logged in the Header
Long register and not issued as an Error Message to RC either.
Reset to 1b.
31:14
Reserved
RO
Reset to 0.
7.2.82
ADVANCE ERROR CAPABILITIES AND CONTROL REGISTER – OFFSET
118h
BIT
FUNCTION
TYPE
DESCRIPTION
4:0
First Error Pointer
ROS
It indicates the bit position of the first error reported in the Uncorrectable
Error Status register.
Reset to 00000b.
5
ECRC Generation
Capable
RO
When set, it indicates the Switch has the capability to generate ECRC.
Reset to 1b.
6
ECRC Generation
Enable
RWS
When set, it enables the generation of ECRC when needed.
Reset to 0b.
7
ECRC Check
Capable
RO
When set, it indicates the Switch has the capability to check ECRC.
Reset to 1b.
8
ECRC Check Enable
RWS
When set, the function of checking ECRC is enabled.
Reset to 0b.
31:9
Reserved
RO
Reset to 0.
7.2.83
HEADER LOG REGISTER – OFFSET From 11Ch to 128h
BIT
FUNCTION
TYPE
DESCRIPTION
31:0
1st DWORD
ROS
Hold the 1st DWORD of TLP Header. The Head byte is in big endian.
63:32
2nd DWORD
ROS
Hold the 2nd DWORD of TLP Header. The Head byte is in big endian.
95:64
3rd DWORD
ROS
Hold the 3rd DWORD of TLP Header. The Head byte is in big endian.
127:96
4th DWORD
ROS
Hold the 4th DWORD of TLP Header. The Head byte is in big endian.
7.2.84
PCI EXPRESS VIRTUAL CHANNEL CAPABILITY ID REGISTER – OFFSET
140h
BIT
FUNCTION
TYPE
DESCRIPTION
15:0
Extended
Capabilities ID
RO
Read as 0002h to indicate that these are PCI express extended capability
registers for virtual channel.
7.2.85
CAPABILITY VERSION – OFFSET 140h
BIT
FUNCTION
TYPE
DESCRIPTION
19:16
Capability Version
RO
Read as 1h. Indicates PCIe Base Specification REV. 1.0a.
Reset to 1h.
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