TM Family Datasheet Page 5 of 79 June 2009 – R" />
參數(shù)資料
型號： PI7C9X20404GPBNBE
廠商： Pericom
文件頁數(shù)： 45/79頁
文件大?。?/td> 0K
描述： IC PCIE PACKET SWITCH 148LFBGA
產(chǎn)品變化通告： Product Discontinuation Notice 22/Jan/2010
標準包裝： 189
系列： GreenPacket™
應(yīng)用： 封裝開關(guān)，4 端口/4 線道
接口： PCI Express
封裝/外殼： 148-LFBGA
供應(yīng)商設(shè)備封裝： 148-LFBGA（12x12）
包裝： 托盤
安裝類型： 表面貼裝
PI7C9X20404GP
4Port-4Lane PCI Express Switch
GreenPacket
TM Family
Datasheet
Page 5 of 79
June 2009 – Revision 1.6
Pericom Semiconductor
TABLE OF CONTENTS
1
FEATURES.........................................................................................................................................................10
2
GENERAL DESCRIPTION..............................................................................................................................11
3
PIN DESCRIPTION...........................................................................................................................................12
3.1
PCI EXPRESS INTERFACE SIGNALS ....................................................................................................12
3.2
PORT CONFIGURATION SIGNALS .......................................................................................................12
3.3
HOT PLUG SIGNALS ...............................................................................................................................13
3.4
MISCELLANEOUS SIGNALS..................................................................................................................13
3.5
JTAG BOUNDARY SCAN SIGNALS ......................................................................................................14
3.6
POWER PINS.............................................................................................................................................14
4
PIN ASSIGNMENTS .........................................................................................................................................15
4.1
PIN LIST OF 148-PIN LFBGA....................................................................................................................15
5
FUNCTIONAL DESCRIPTION.......................................................................................................................16
5.1
PHYSICAL LAYER CIRCUIT ..................................................................................................................16
5.2
DATA LINK LAYER (DLL)......................................................................................................................18
5.3
TRANSACTION LAYER RECEIVE BLOCK (TLP DECAPSULATION) ..............................................18
5.4
ROUTING ..................................................................................................................................................18
5.5
TC/VC MAPPING......................................................................................................................................19
5.6
QUEUE.......................................................................................................................................................19
5.6.1
PH ....................................................................................................................................................... 19
5.6.2
PD ....................................................................................................................................................... 19
5.6.3
NPHD ................................................................................................................................................. 19
5.6.4
CPLH .................................................................................................................................................. 19
5.6.5
CPLD .................................................................................................................................................. 20
5.7
TRANSACTION ORDERING...................................................................................................................20
5.8
PORT ARBITRATION ..............................................................................................................................21
5.9
VC ARBITRATION ...................................................................................................................................21
5.10
FLOW CONTROL .....................................................................................................................................21
5.11
TRANSATION LAYER TRANSMIT BLOCK (TLP ENCAPSULATION) .............................................21
6
EEPROM INTERFACE AND SYSTEM MANAGEMENT BUS..................................................................22
6.1
EEPROM INTERFACE .............................................................................................................................22
6.1.1
AUTO MODE EERPOM ACCESS ..................................................................................................... 22
6.1.2
EEPROM MODE AT RESET .............................................................................................................. 22
6.1.3
EEPROM SPACE ADDRESS MAP .................................................................................................... 22
6.1.4
MAPPING EEPROM CONTENTS TO CONFIGURATION REGISTERS.......................................... 24
6.2
SMBUS INTERFACE .................................................................................................................................29
7
REGISTER DESCRIPTION .............................................................................................................................30
7.1
REGISTER TYPES ....................................................................................................................................30
7.2
TRANSPARENT MODE CONFIGURATION REGISTERS....................................................................30
7.2.1
VENDOR ID REGISTER – OFFSET 00h ........................................................................................... 32
7.2.2
DEVICE ID REGISTER – OFFSET 00h............................................................................................. 32
7.2.3
COMMAND REGISTER – OFFSET 04h ............................................................................................ 32
7.2.4
PRIMARY STATUS REGISTER – OFFSET 04h................................................................................. 33
7.2.5
REVISION ID REGISTER – OFFSET 08h ......................................................................................... 33
相關(guān)PDF資料
PDF描述
PI7C9X20404SLCFDE IC PCIE PACKET SWITCH 128LQFP
PI7C9X20505GPBNDE IC PCIE PACKET SWITCH 256BGA
PI7C9X20508GPBNDE IC PCIE PACKET SWITCH 256BGA
PI7C9X440SLBFDE IC PCIE-TO-USB 2.0 CTRLR 128LQFP
PI7C9X442SLBFDE IC PCIE-TO-USB2.0 SWIDGE 128LQFP
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
PI7C9X20404SLCEVB 制造商:Pericom Semiconductor Corporation 功能描述:PCIE 4 PORT SWITCH EVAL BOARD - Boxed Product (Development Kits)
PI7C9X20404SLCFDE 功能描述:外圍驅(qū)動器與原件 - PCI 4port 4lane PCIe Packet Switch RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray
PI7C9X20404SLCFDEX 功能描述:外圍驅(qū)動器與原件 - PCI 4port 4lane PCIe Packet Switch RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray
PI7C9X20505GPBNDE 功能描述:外圍驅(qū)動器與原件 - PCI 5port 5lane PCIe PacketSwitch RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray
PI7C9X20508GPANDE 制造商:Pericom Semiconductor Corporation 功能描述:5-PORT, 8-LANE, GREENPACKET- PCIE PACKET SWITCH - Rail/Tube
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*