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參數(shù)資料
| 型號： | PI7C9X20404GPBNBE |
| 廠商： | Pericom |
| 文件頁數(shù)： | 19/79頁 |
| 文件大小： | 0K |
| 描述： | IC PCIE PACKET SWITCH 148LFBGA |
| 產(chǎn)品變化通告： | Product Discontinuation Notice 22/Jan/2010 |
| 標(biāo)準(zhǔn)包裝： | 189 |
| 系列： | GreenPacket™ |
| 應(yīng)用： | 封裝開關(guān)，4 端口/4 線道 |
| 接口： | PCI Express |
| 封裝/外殼： | 148-LFBGA |
| 供應(yīng)商設(shè)備封裝： | 148-LFBGA（12x12） |
| 包裝： | 托盤 |
| 安裝類型： | 表面貼裝 |
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PI7C9X20404GP
4Port-4Lane PCI Express Switch
GreenPacket
TM Family
Datasheet
Page 26 of 79
June 2009 – Revision 1.6
Pericom Semiconductor
ADDRESS
PCI CFG
OFFSET
DESCRIPTION
154h (Port 0)
154h: Bit [7:1]
VC0 TC/VC Map for Port 0
Bit [15:9]: When set, it indicates the corresponding TC is
mapped into VC0
E0h (Port1)
E0h: Bit [24]
F0h (Port 1)
F0h: Bit [28]
80h (Port 1)
80h: Bit[21]
144h (Port 1)
144h: Bit [4]
ECh (Port 1)
ECh: Bit [25:24]
PCIe Capability Slot Implemented for Port 1
Bit [0]: When set, the slot is implemented for Port 1
Slot Clock Configuration for Port 1
Bit [1]: When set, the component uses the clock provided on the
Connector
Device specific Initialization for Port 1
Bit [2]: When set, the DSI is required
LPVC Count for Port 1
Bit [3]: When set, the VC1 is allocated to LPVC of Egress Port 1
Port Number for Port 1
Bit [5:4]: It represents the logic port numbering for physical port
1
22h
154h (Port 1)
154h: Bit [7:1]
VC0 TC/VC Map for Port 1
Bit [15:9]: When set, it indicates the corresponding TC is
mapped into VC0
E0h (Port 2)
E0h: Bit [24]
F0h (Port 2)
F0h: Bit [28]
80h (Port 2)
80h: Bit[21]
144h (Port 2)
144h: Bit [4]
ECh (Port 2)
ECh: Bit [25:24]
PCIe Capability Slot Implemented for Port 2
Bit [0]: When set, the slot is implemented for Port 2
Slot Clock Configuration for Port 2
Bit [1]: When set, the component uses the clock provided on the
Connector
Device specific Initialization for Port 2
Bit [2]: When set, the DSI is required
LPVC Count for Port 2
Bit [3]: When set, the VC1 is allocated to LPVC of Egress Port 2
Port Number for Port 2
Bit [5:4]: It represents the logic port numbering for physical port
2
24h
154h (Port 2)
154h: Bit [7:1]
VC0 TC/VC Map for Port 2
Bit [15:9]: When set, it indicates the corresponding TC is
mapped into VC0
E0h (Port 3)
E0h: Bit [24]
F0h (Port 3)
F0h: Bit [28]
80h (Port 3)
80h: Bit[21]
144h (Port 3)
144h: Bit [4]
ECh (Port 3)
ECh: Bit [25:24]
PCIe Capability Slot Implemented for Port 3
Bit [0]: When set, the slot is implemented for Port 3
Slot Clock Configuration for Port 3
Bit [1]: When set, the component uses the clock provided on the
Connector
Device specific Initialization for Port 3
Bit [2]: When set, the DSI is required
LPVC Count for Port 3
Bit [3]: When set, the VC1 is allocated to LPVC of Egress Port 3
Port Number for Port 3
Bit [5:4]: It represents the logic port numbering for physical port
3
26h
154h (Port 3)
154h: Bit [7:1]
VC0 TC/VC Map for Port 3
Bit [15:9]: When set, it indicates the corresponding TC is
mapped into VC0
32h
F4h (Port 1)
F4h: Bit [15:0]
Slot Capability 0 of Port 1
Bit [15:0]: Mapping to the low word of slot capability register
34h
F4h (Port 2)
F4h: Bit [15:0]
Slot Capability 0 of Port 2
Bit [15:0]: Mapping to the low word of slot capability register
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| PI7C9X20404SLCEVB | 制造商:Pericom Semiconductor Corporation 功能描述:PCIE 4 PORT SWITCH EVAL BOARD - Boxed Product (Development Kits) |
| PI7C9X20404SLCFDE | 功能描述:外圍驅(qū)動器與原件 - PCI 4port 4lane PCIe Packet Switch RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| PI7C9X20404SLCFDEX | 功能描述:外圍驅(qū)動器與原件 - PCI 4port 4lane PCIe Packet Switch RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| PI7C9X20505GPBNDE | 功能描述:外圍驅(qū)動器與原件 - PCI 5port 5lane PCIe PacketSwitch RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| PI7C9X20508GPANDE | 制造商:Pericom Semiconductor Corporation 功能描述:5-PORT, 8-LANE, GREENPACKET- PCIE PACKET SWITCH - Rail/Tube |
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