TM Family Datasheet Page 33 of 79 June 2009 – " />
參數(shù)資料
型號： PI7C9X20404GPBNBE
廠商： Pericom
文件頁數(shù)： 27/79頁
文件大?。?/td> 0K
描述： IC PCIE PACKET SWITCH 148LFBGA
產(chǎn)品變化通告： Product Discontinuation Notice 22/Jan/2010
標(biāo)準(zhǔn)包裝： 189
系列： GreenPacket™
應(yīng)用： 封裝開關(guān)，4 端口/4 線道
接口： PCI Express
封裝/外殼： 148-LFBGA
供應(yīng)商設(shè)備封裝： 148-LFBGA（12x12）
包裝： 托盤
安裝類型： 表面貼裝
PI7C9X20404GP
4Port-4Lane PCI Express Switch
GreenPacket
TM Family
Datasheet
Page 33 of 79
June 2009 – Revision 1.6
Pericom Semiconductor
BIT
FUNCTION
TYPE
DESCRIPTION
15:11
Reserved
RO
Reset to 0b.
7.2.4
PRIMARY STATUS REGISTER – OFFSET 04h
BIT
FUNCTION
TYPE
DESCRIPTION
18:16
Reserved
RO
Reset to 000b.
19
Interrupt Status
RO
Indicates that an INTx Interrupt Message is pending internally to the device.
In the Switch, the forwarding of INTx messages from the downstream device
of the Switch port is not reflected in this bit. Must be hardwired to 0b.
20
Capabilities List
RO
Set to 1 to enable support for the capability list (offset 34h is the pointer to
the data structure).
Reset to 1b.
21
66MHz Capable
RO
Does not apply to PCI Express. Must be hardwired to 0b.
22
Reserved
RO
Reset to 0b.
23
Fast Back-to-Back
Capable
RO
Does not apply to PCI Express. Must be hardwired to 0b.
24
Master Data Parity
Error
RWC
Set to 1 (by a requester) whenever a Parity error is detected or forwarded on
the primary side of the port in a Switch.
If the Parity Error Response Enable bit is cleared, this bit is never set.
Reset to 0b.
26:25
DEVSEL# timing
RO
Does not apply to PCI Express. Must be hardwired to 0b.
27
Signaled Target
Abort
RO
Set to 1 (by a completer) whenever completing a request on the primary side
using the Completer Abort Completion Status.
Reset to 0b.
28
Received Target
Abort
RO
Set to 1 (by a requestor) whenever receiving a Completion with Completer
Abort Completion Status on the primary side.
Reset to 0b.
29
Received Master
Abort
RO
Set to 1 (by a requestor) whenever receiving a Completion with Unsupported
Request Completion Status on primary side.
Reset to 0b.
30
Signaled System
Error
RWC
Set to 1 when the Switch sends an ERR_FATAL or ERR_NONFATAL
Message, and the SERR Enable bit in the Command register is 1.
Reset to 0b.
31
Detected Parity Error
RWC
Set to 1 whenever the primary side of the port in a Switch receives a Poisoned
TLP.
Reset to 0b.
7.2.5
REVISION ID REGISTER – OFFSET 08h
BIT
FUNCTION
TYPE
DESCRIPTION
7:0
Revision
RO
Indicates revision number of device. Hardwired to 01h.
7.2.6
CLASS CODE REGISTER – OFFSET 08h
BIT
FUNCTION
TYPE
DESCRIPTION
15:8
Programming
Interface
RO
Read as 00h to indicate no programming interfaces have been defined for
PCI-to-PCI Bridges.
23:16
Sub-Class Code
RO
Read as 04h to indicate device is a PCI-to-PCI Bridge.
31:24
Base Class Code
RO
Read as 06h to indicate device is a Bridge device.
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