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| 型號(hào)： | PI7C9X20404GPBNBE |
| 廠商： | Pericom |
| 文件頁數(shù)： | 48/79頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC PCIE PACKET SWITCH 148LFBGA |
| 產(chǎn)品變化通告： | Product Discontinuation Notice 22/Jan/2010 |
| 標(biāo)準(zhǔn)包裝： | 189 |
| 系列： | GreenPacket™ |
| 應(yīng)用： | 封裝開關(guān)，4 端口/4 線道 |
| 接口： | PCI Express |
| 封裝/外殼： | 148-LFBGA |
| 供應(yīng)商設(shè)備封裝： | 148-LFBGA（12x12） |
| 包裝： | 托盤 |
| 安裝類型： | 表面貼裝 |
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PI7C9X20404GP
4Port-4Lane PCI Express Switch
GreenPacket
TM Family
Datasheet
Page 52 of 79
June 2009 – Revision 1.6
Pericom Semiconductor
BIT
FUNCTION
TYPE
DESCRIPTION
14:12
L0s Exit Latency
RO
Indicates the L0s exit latency for the given PCIe Link.
The length of time this port requires to complete transition from L0s to L0 is
in the range of 256ns to less than 512ns. The default value may be changed
by SMBus or auto-loading from EEPROM.
Reset to 011b.
17:15
L1 Exit
Latency
RO
Indicates the L1 exit latency for the given PCIe Link.
The length of time this port requires to complete transition from L1 to L0 is in
the range of 16us to less than 32us. The default value may be changed by
SMBus or auto-loading from EEPROM.
Reset to 000b.
19:18
Reserved
RO
Reset to 00b.
20
Data Link Layer
Active Reporting
Capable
RO
For a Downstream Port, this bit must be set to 1b if the component supports
the optional capability of reporting the DL_Active state of the Data Link
Control and Management State Machine. For a hot-plug capable Downstream
Port, this bit must be set to 1b.
For Upstream Port, this bit must be hardwired to 0b.
Reset to 0b for upstream port.
Reset to 1b for downstream ports.
23:21
Reserved
R0
Reset to 000b
31:24
Port Number
RO
Indicates the PCIe Port Number for the given PCIe Link. The default value
may be changed by SMBus or auto-loading from EEPROM.
Reset to 00h for Port 0.
Reset to 01h for Port 1.
Reset to 02h for Port 2.
Reset to 03h for Port 3.
7.2.69
LINK CONTROL REGISTER – OFFSET F0h
BIT
FUNCTION
TYPE
DESCRIPTION
1:0
Active State Power
Management
(ASPM) Control
RW
00b: ASPM is Disabled
01b: L0s Entry Enabled
10b: L1 Entry Enabled
11b: L0s and L1 Entry Enabled
Note that the receiver must be capable of entering L0s even when the field is
disabled.
Reset to 00b.
2
Reserved
RO
Reset to 0b.
3
Read Completion
Boundary (RCB)
RO
Does not apply to PCI Express Switch. Returns ‘0’ when read.
Reset to 0b.
4
Link Disable
RW
At upstream port, it is not allowed to disable the link, so this bit is hardwired
to ‘0’. For downstream ports, it disables the link when this bit is set.
Reset to 0b.
5
Retrain Link
RW
At upstream port, it is not allowed to retrain the link, so this bit is hardwired
to 0b. For downstream ports, it initiates Link Retraining when this bit is set.
This bit always returns 0b when read.
6
Common Clock
Configuration
RW
0b: The components at both ends of a link are operating with asynchronous
reference clock
1b: The components at both ends of a link are operating with a distributed
common reference clock
Reset to 0b.
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