參數(shù)資料
型號(hào)： PCD5003A
廠商： NXP Semiconductors N.V.
英文描述： Enhanced Pager Decoder for POCSAG
中文描述： 增強(qiáng)傳呼機(jī)POCSAG碼解碼器
文件頁(yè)數(shù)： 9/44頁(yè)
文件大?。?/td> 233K
代理商： PCD5003A
1999 Jan 08
9
Philips Semiconductors
Product specification
Enhanced Pager Decoder for POCSAG
PCD5003A
7.8
Bit rates
The PCD5003A can be configured for data rates of 512,
1200 or 2400 bits/s by SPF programming. These data
rates are derived from a single 76.8 kHz oscillator
frequency.
7.9
Oscillator
The oscillator circuit is designed to operate at 76.8 kHz.
Typically, a tuning fork crystal will be used as a frequency
source. Alternatively, an external clock signal can be
applied to pin XTAL1 (amplitude = V
DD
to V
SS
), but a
slightly higher oscillator current is consumed. A 2.2 M
feedback resistor connected between XTAL1 and XTAL2
is required for proper operation.
To allow easy oscillator adjustment (e.g. by means of a
variable capacitor) a 32.768 kHz reference frequency can
be selected at output REF by SPF programming.
7.10
Input data processing
Data input is binary and fully asynchronous. Input bit rates
of 512, 1200 and 2400 bits/s are supported. As a
programmable option, the polarity of the received data can
be inverted before further processing.
The input data is noise filtered by means of a digital filter.
Data is sampled at 16 times the data rate and averaged by
majority decision.
The filtered data is used to synchronize an internal clock
generator by monitoring transitions. The recovered clock
phase can be adjusted in steps of
1
8
or
1
32
bit period per
received bit.
The larger step size is used when bit synchronization has
not been achieved, the smaller when a valid data
sequence has been detected (e.g. preamble or sync
word).
7.11
Battery saving
Current consumption is reduced by switching off internal
decoder sections whenever the receiver is not enabled.
To further increase battery efficiency, reception and
decoding of an address code-word is stopped as soon as
the uncorrected address field differs by more than 3 bits
from the enabled RICs. If the next code-word must be
received again, the receiver is re-enabled thus observing
the programmed establishment times t
RXE
and t
RDE
.
The current consumption of the complete pager can be
minimized by separately activating the RF oscillator circuit
(at output ROE) before activating the rest of the receiver.
This is possible with the UAA2082 receiver which has
external biasing for the oscillator circuit.
7.12
Synchronization strategy
In ON status the PCD5003A synchronizes to the POCSAG
data stream by means of the Philips ACCESS
algorithm.
A flow diagram is shown in Fig.4. Where ‘sync word’ is
used, this implies both the standard POCSAG sync word
and any enabled User Programmable Sync Word
(UPSW).
Several modes of operation can be distinguished
depending on the synchronization state. Each mode uses
a different method to obtain or retain data synchronization.
The receiver and oscillator enable outputs (respectively
RXE and ROE) are switched accordingly, with the
appropriate establishment times (respectively t
RXON
and
t
ROON
).
Before comparing received data with preamble, an
enabled sync word or programmed user addresses, the
appropriate error correction is applied.
Initially, after switching to ON status, the decoder is in
switch-on
mode. Here the receiver will be enabled for a
period up to 3 batches, testing for preamble and sync
word. Failure to detect preamble or sync word will cause
switching to ‘carrier off’ mode.
Detection of preamble switches to
preamble receive
mode, in which sync word is looked for. The receiver will
remain enabled while preamble is detected. When neither
sync word nor preamble is found within 1 batch duration
‘carrier off’ mode is entered.
Upon detection of a sync word the
data receive
mode is
entered. The receiver is activated only during enabled user
address frames and sync word periods. When an enabled
user address has been detected, the receiver will be kept
enabled for message code-word reception until the call
termination criteria are met.
During call reception data bytes are stored in an internal
SRAM buffer, capable of storing 2 batches of message
data.
Messages are transmitted contiguously, only interrupted
by sync words at the beginning of each batch. When a
message extends beyond the end of a batch, no testing for
sync takes place. Instead, a message data transfer will be
initiated by an interrupt to the external controller. Data
reception continues normally after a period corresponding
to the sync word duration.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
PCD5003AH 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Enhanced Pager Decoder for POCSAG
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PCD5003U/10 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Advanced POCSAG Paging Decoder
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