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參數(shù)資料
| 型號： | PCD5003A |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Enhanced Pager Decoder for POCSAG |
| 中文描述： | 增強傳呼機POCSAG碼解碼器 |
| 文件頁數(shù)： | 20/44頁 |
| 文件大?。?/td> | 233K |
| 代理商： | PCD5003A |
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1999 Jan 08
20
Philips Semiconductors
Product specification
Enhanced Pager Decoder for POCSAG
PCD5003A
7.29
Pending interrupts
A secondary status register is used for storing status bits
of pending interrupts. This occurs:
When a new call is received while the previous one was
not yet acknowledged by reading the status register
When an interrupt occurs during a status read operation.
After completion of the status read the primary register is
loaded with the contents of the secondary register, which
is then reset. Next, an immediate interrupt is generated,
output INT becoming active 1 decoder clock cycle after it
was reset following the status read.
Remark
: In the event of multiple pending calls, only the
status bits of the last call are retained.
7.30
Out-of-range Indication
The out-of-range condition occurs when entering fade
recovery or ‘carrier off’ mode. This condition is reflected in
bit D5 of the status register. The out-of-range condition is
reset when either preamble or a valid sync word is
detected.
The out-of-range bit (D5) in the status register is updated
each time the receiver is disabled (RXE
↓
0). Every
change of state in bit D5 generates an interrupt.
7.31
Real-time clock
The PCD5003A provides a periodic reference pulse at
output REF. The frequency of this signal can be selected
by SPF programming:
32768 Hz
50 Hz (square-wave)
2 Hz
1
60
Hz.
The 32768 Hz signal does not have a fixed period:
it consists of 32 pulses distributed over 75 main oscillator
cycles at 76.8 kHz. The timing is shown in Fig.15.
When programmed for
1
60
Hz (1 pulse per minute) the
pulse at output REF is held off while the receiver is
enabled.
Except for the 50 Hz frequency the pulse width t
RFP
is
equal to one decoder clock period.
The real-time clock counter runs continuously irrespective
of the operating condition of the PCD5003A. It contains a
seconds register
(maximum 59) and a
1
100
second
register
(maximum 99), which can be read or written via
the I
2
C-bus. The bit allocation of both registers is shown in
Tables 16 and 17.
Table 16
Real-time clock; seconds register (01H;
read/write)
Table 17
Real-time clock;
1
100
second register (02H;
read/write)
7.32
Periodic interrupt
A periodic interrupt can be realised with the periodic
interrupt counter. This 8-bit counter is incremented every
1
100
second and produces an interrupt when it reaches the
value stored in the periodic interrupt modulus register.
The counter register is then reset and counting continues.
Operation is started by writing a non-zero value to the
modulus register. Writing a zero will stop interrupt
generation immediately and will halt the periodic interrupt
counter after 2.55 seconds.
The modulus register is write-only, the counter register can
only be read. Both registers have the same index
address (05H).
BIT
(MSB: D7)
VALUE
DESCRIPTION
D0
D1
D2
D3
D4
D5
D6
X
1 s
2 s
4 s
8 s
16 s
32 s
not used: ignored when written;
undetermined when read
not used: ignored when written;
undetermined when read
D7
X
BIT
(MSB: D7)
VALUE
DESCRIPTION
D0
D1
D2
D3
D4
D5
D6
D7
X
0.01 s
0.02 s
0.04 s
0.08 s
0.16 s
0.32 s
0.64 s
not used: ignored when written;
undetermined when read
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| PCD5003AH | Enhanced Pager Decoder for POCSAG |
| PCD5003 | Advanced POCSAG Paging Decoder |
| PCD5003H | Advanced POCSAG Paging Decoder |
| PCD5008 | FLEX Pager Decoder |
| PCD5008H | FLEX Pager Decoder |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PCD5003AH | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Enhanced Pager Decoder for POCSAG |
| PCD5003H | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Advanced POCSAG Paging Decoder |
| PCD5003HB-T | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Telecommunication Decoder |
| PCD5003U/10 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Advanced POCSAG Paging Decoder |
| PCD5008 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:FLEX Pager Decoder |
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