參數(shù)資料
型號: PCD5003A
廠商: NXP Semiconductors N.V.
英文描述: Enhanced Pager Decoder for POCSAG
中文描述: 增強(qiáng)傳呼機(jī)POCSAG碼解碼器
文件頁數(shù): 27/44頁
文件大小: 233K
代理商: PCD5003A
1999 Jan 08
27
Philips Semiconductors
Product specification
Enhanced Pager Decoder for POCSAG
PCD5003A
Table 22
Establishment time as a function of bit rate
Table 23
Special programmed functions (EEPROM address 02H)
Table 24
Special programmed functions (EEPROM address 03H)
NOMINAL
ESTABLISHMENT
TIME
ACTUAL ESTABLISHMENT TIME
512 BITS/s
1024 BITS/s
1200 BITS/s
2400 BITS/s
5 ms
10 ms
15 ms
20 ms
30 ms
40 ms
50 ms
5.9 ms (3 bits)
11.7 ms (6 bits)
15.6 ms (8 bits)
23.4 ms (12 bits)
31.2 ms (16 bits)
39.1 ms (20 bits)
46.9 ms (24 bits)
5.9 ms (6 bits)
11.7 ms (12 bits)
15.6 ms (16 bits)
23.4 ms (24 bits)
31.2 ms (32 bits)
39.1 ms (40 bits)
46.9 ms (48 bits)
5.0 ms (6 bits)
10.0 ms (12 bits)
16.7 ms (20 bits)
20.0 ms (24 bits)
26.7 ms (32 bits)
40.0 ms (48 bits)
53.3 ms (64 bits)
5.0 ms (12 bits)
10.0 ms (24 bits)
16.7 ms (40 bits)
20.0 ms (48 bits)
26.7 ms (64 bits)
40.0 ms (96 bits)
53.3 ms (128 bits)
BIT (MSB: D7)
VALUE
DESCRIPTION
D0
D1
X
X
not used
not used
32768 Hz real-time clock reference
50 Hz square wave
2 Hz
1
60
Hz
signal test mode enabled (REF and INT outputs)
burst error correction enabled
reserved for future use
D3 and D2
0 0
0 1
1 0
1 1
1
0
X X
D4
D5
D7 and D6
BIT (MSB: D7)
VALUE
DESCRIPTION
D1 and D0
0 0
0 1
1 0
1 1
1
X
X
0
1
0
1
0
1
2048 Hz acoustic alerter frequency
2731 Hz acoustic alerter frequency
4096 Hz acoustic alerter frequency
3200 Hz acoustic alerter frequency
automatic POCSAG alert generation enabled
not used
not used
DQC mode 0
DQC mode 1
INT output polarity: active LOW
INT output polarity: active HIGH
standard call termination
enhanced call termination
D2
D3
D4
D5
D6
D7
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