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參數(shù)資料
| 型號： | PCD5003A |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Enhanced Pager Decoder for POCSAG |
| 中文描述： | 增強傳呼機POCSAG碼解碼器 |
| 文件頁數(shù)： | 15/44頁 |
| 文件大小： | 233K |
| 代理商： | PCD5003A |
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1999 Jan 08
15
Philips Semiconductors
Product specification
Enhanced Pager Decoder for POCSAG
PCD5003A
Table 11
Receiver and oscillator establishment times
(note 1)
Note
1.
The exact values may differ slightly from the above
values, depending on the bit rate (see Table 22).
7.23
Synthesizer control
Control of an external frequency synthesizer is possible
via a dedicated 3-line serial interface (outputs ZSD,
ZSC and ZLE). This interface is common to a number of
available synthesizers. The synthesizer is enabled using
the oscillator enable output ROE.
The frequency parameters must be programmed in
EEPROM. Two blocks of maximum 24 bits each can be
stored. Any unused bits must be programmed at the
beginning of a block: only the last bits are used by the
synthesizer.
When the function is selected by SPF programming
(SPF byte 01, bit D6), data is transferred to the
synthesizer each time the PCD5003A is switched from
OFF to ON status. Transfer takes place serially in two
blocks, starting with bit 0 (MSB) of block 1 (see Table 25).
Data bits on ZSD change on the falling flanks of ZSC. After
clocking all bits into the synthesizer, a latch enable pulse
copies the data to the internal divider registers. A timing
diagram is given in Fig.6.
The data output timing is synchronous, but has a pause in
the bit stream of each block. This pause occurs in the
13th bit while ZSC is LOW. The nominal pause duration t
p
depends on the programmed bit rate for data reception
and is shown in Table 12. The total duration of the 13th bit
is given by t
ZCL
+ t
p
.
A similar pause occurs between the first and the second
data block. The delay between the first latch enable pulse
and the second data block is given by t
ZDL2
+ t
p
.
The complete start-up timing of the synthesizer interface is
given in Fig.13.
CONTROL
OUTPUT
ESTABLISHMENT TIME
UNIT
RXE
ROE
5
20
10
30
15
40
30
50
ms
ms
Table 12
Synthesizer programming pause
7.24
Serial microcontroller interface
The PCD5003A has an I
2
C-bus serial microcontroller
interface capable of operating at 400 kbits/s.
The PCD5003A is a slave transceiver with a 7-bit I
2
C-bus
address 39 (bits A6 to A0 = 0100111). Together with the
R/W bit the first byte of an I
2
C-bus message then becomes
4EH (write) or 4FH (read).
Data transmission requires 2 lines: SDA (serial data) and
SCL (serial clock), each with an external pull-up resistor.
The clock signal (SCL) for any data transmission must be
generated by the external controlling device.
A transmission is initiated by a START condition
(S: SCL = 1, SDA =
↓
) and terminated by a STOP
condition (P: SCL = 1, SDA =
↑
).
Data bits must be stable when SCL is HIGH. If there are
multiple transmissions, the STOP condition can be
replaced with a new START condition.
Data is transferred on a byte basis, starting with a device
address and a read/write indicator. Each transmitted byte
must be followed by an acknowledge bit ACK
(active LOW). If a receiving device is not ready to accept
the next complete byte, it can force a bus wait state by
holding SCL LOW.
The general I
2
C-bus transmission format is shown in Fig.7.
Formats for master/slave communication are shown in
Fig.8.
BIT RATE (bit/s)
t
p
(CLOCKS)
119
33
1
t
p
(
μ
s)
1549
430
13
512
1200
2400
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|---|---|
| PCD5003AH | Enhanced Pager Decoder for POCSAG |
| PCD5003 | Advanced POCSAG Paging Decoder |
| PCD5003H | Advanced POCSAG Paging Decoder |
| PCD5008 | FLEX Pager Decoder |
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| PCD5003AH | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Enhanced Pager Decoder for POCSAG |
| PCD5003H | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Advanced POCSAG Paging Decoder |
| PCD5003HB-T | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Telecommunication Decoder |
| PCD5003U/10 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Advanced POCSAG Paging Decoder |
| PCD5008 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:FLEX Pager Decoder |
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