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參數(shù)資料
| 型號： | PCD5003A |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Enhanced Pager Decoder for POCSAG |
| 中文描述： | 增強傳呼機POCSAG碼解碼器 |
| 文件頁數(shù)： | 26/44頁 |
| 文件大?。?/td> | 233K |
| 代理商： | PCD5003A |
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1999 Jan 08
26
Philips Semiconductors
Product specification
Enhanced Pager Decoder for POCSAG
PCD5003A
Table 19
Unused EEPROM addresses
Note
1.
When using bytes 04H and 05H, care must be taken
to preserve the SPF information stored in
bytes 00H to 03H.
ROW
HEX
0
5
6
7
04 and 05
(1)
28 to 2D
30 to 35
38 to 3D
7.57
Special programmed function allocation
The SPF bit allocation in the EEPROM is shown in
Tables 20 to 24. The SPF bits are located in row 0 of the
EEPROM and occupy 4 bytes.
Bytes 04H and 05H are not used and are available for
general purpose storage.
The contents of SPF (bytes 0 to 3) are read into the
associated logic only when the decoder is reset
(HIGH level in input RST).
Table 20
Special programmed functions (EEPROM address 00H)
Table 21
Special programmed functions (EEPROM address 01H)
Note
1.
Since the exact establishment time is related to the programmed bit rate, Table 22 shows the values for the various
bit rates.
BIT (MSB: D7)
VALUE
DESCRIPTION
D0
D1
D2
D3
D4
D5
D6
D7
X
X
X
X
X
X
X
1
reserved for future use; logic 0 when read
reserved for future use
reserved for future use
reserved for future use
reserved for future use
reserved for future use
reserved for future use; logic 0 when read
received data inversion enabled
BIT (MSB: D7)
VALUE
DESCRIPTION
D1 and D0
0 0
0 1
1 0
1 1
0 0
0 1
1 0
1 1
0 0
0 1
1 0
1 1
1
5 ms receiver establishment time (nominal); note 1
10 ms receiver establishment time (nominal); note 1
15 ms receiver establishment time (nominal); note 1
30 ms receiver establishment time (nominal); note 1
20 ms oscillator establishment time (nominal); note 1
30 ms oscillator establishment time (nominal); note 1
40 ms oscillator establishment time (nominal); note 1
50 ms oscillator establishment time (nominal); note 1
512 bits/s received bit rate
1024 bits/s (not used in POCSAG)
1200 bits/s
2400 bits/s
synthesizer interface enabled (data is output via ZSD, ZSC and ZLE at
decoder switch-on)
voltage converter enabled
D3 and D2
D5 and D4
D6
D7
1
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| PCD5003AH | Enhanced Pager Decoder for POCSAG |
| PCD5003 | Advanced POCSAG Paging Decoder |
| PCD5003H | Advanced POCSAG Paging Decoder |
| PCD5008 | FLEX Pager Decoder |
| PCD5008H | FLEX Pager Decoder |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PCD5003AH | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Enhanced Pager Decoder for POCSAG |
| PCD5003H | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Advanced POCSAG Paging Decoder |
| PCD5003HB-T | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Telecommunication Decoder |
| PCD5003U/10 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Advanced POCSAG Paging Decoder |
| PCD5008 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:FLEX Pager Decoder |
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