參數(shù)資料
型號: PCD5003A
廠商: NXP Semiconductors N.V.
英文描述: Enhanced Pager Decoder for POCSAG
中文描述: 增強(qiáng)傳呼機(jī)POCSAG碼解碼器
文件頁數(shù): 28/44頁
文件大?。?/td> 233K
代理商: PCD5003A
1999 Jan 08
28
Philips Semiconductors
Product specification
Enhanced Pager Decoder for POCSAG
PCD5003A
7.58
Synthesizer programming data
Data for programming a PLL synthesizer via pins ZSD,
ZSC and ZLE can be stored in row 1 of the EEPROM.
Six bytes are available starting from address 08H.
Data is transferred in two serial blocks of 24 bits each,
starting with bit 0 (MSB) of block 1. Any unused bits must
be programmed at the beginning of a block.
7.59
Identifier storage allocation
Up to 6 different identifiers can be stored in EEPROM for
matching with incoming data. The PCD5003A can
distinguish two types of identifiers:
User addresses (RIC)
User Programmable Sync Words (UPSW).
Identifiers are stored in EEPROM rows 2, 3 and 4. Each
identifier location consists of 3 bytes in the same column.
The identifier number is equal to the column number + 1.
Only the last 4 identifiers (numbers 3 to 6) can be
programmed as a UPSW. Identifiers 1 and 2 always
represent RICs. A UPSW represents an unused address
and must differ by more than 6 bits from preamble to
guarantee detection.
The standard POCSAG sync word is always enabled and
has identifier number 7.
Table 26 shows the memory locations of the 6 identifiers.
The bit allocation per identifier is given in Table 27.
Table 25
Synthesizer programming data (EEPROM address 08H to 0DH)
Table 26
Identifier storage allocation (EEPROM address 10H to 25H)
ADDRESS (HEX)
BIT (MSB: D7)
DESCRIPTION
08
09
0A
0B
0C
0D
D7 to D0
D7 to D0
D7 to D0
D7 to D0
D7 to D0
D7 to D0
bits 0 to 7 of data block 1 (bit 0 is MSB)
bits 8 to 15
bits 16 to 23
bits 0 to 7 of data block 2 (bit 0 is MSB)
bits 8 to 15
bits 16 to 23
ADDRESS (HEX)
BYTE
DESCRIPTION
10 to 15
18 to 1D
20 to 25
1
2
3
identifier number 1 to 6
identifier number 1 to 6
identifier number 1 to 6
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