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參數(shù)資料
| 型號： | PC8265A |
| 英文描述： | PC8265A [Updated 9/03. 59 Pages] |
| 中文描述： | PC8265A [更新9 / 03。 59頁] |
| 文件頁數(shù)： | 51/59頁 |
| 文件大?。?/td> | 455K |
| 代理商： | PC8265A |
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51
PC8265A PowerQUICC II
5336A–HIREL–08/03
Notes:
1. Input clock frequency is given only for the purpose of reference. User should set MODCK_H–MODCK_L so that the result-
ing configuration does not exceed the frequency rating of the user’s part.
Example. If a part is rated at 266 MHz CPU, 200 MHz CPM, and 66 MHz bus, any of the following are possible (note
that the three input clock frequencies are only three of many possible input clock frequencies):
1.
66 MHz input clock, MODCK_H–MODCK_L[0111–011] (with a core multiplication factor of 4 and a CPM multi-
plication factor of 3), and PCI_MODCK = 0 (see note 2 below). The resulting configuration equals the part’s
maximum possible frequencies of 266 MHz CPU, 200 MHz CPM, 66 MHz 60x bus, and a PCI frequency of 66
MHz.
2.
50 MHz input clock, MODCK_H–MODCK_L[0111–011], and PCI_MODCK = 0 (see note 2below) to achieve a
configuration of 200 MHz CPU, 150 MHz CPM, 50 MHz 60x bus, and a PCI frequency of 50 MHz.
3.
40 MHz input clock, MODCK_H–MODCK_L[0010–000], and PCI_MODCK = 0 (see note 2 below) to achieve a
configuration of 200 MHz CPU, 160 MHz CPM, 40 MHz 60x bus, and a PCI frequency of 40 MHz.
Note that with each of the examples, any one of several values for MODCK_H–MODCK_L could possibly be used as
long as the resulting configuration does not exceed the part’s rating.
2. The frequency depends on the value of PCI_MODCK. If PCI_MODCK is high (logic “1“), the PCI frequency is divided by 2
(33 instead of 66 MHz, etc.).
3. In this mode, PCI_MODCK must be “0”
MODCK_H –
MODCK[1–3]
Input Clock
Frequency
(1)
(Bus)
CPM
Multiplication
Factor
CPM
Frequency
Core
Multiplication
Factor
Core
Frequency
PCI Division
Factor
(2)
PCI
Frequency
(2)
1001_011
66 MHz
3.5
233 MHz
4
266 MHz
4/8
58/29 MHz
1001_100
66 MHz
3.5
233 MHz
4.5
300 MHz
4/8
58/29 MHz
1010_000
100 MHz
2
200 MHz
2
200 MHz
3/6
66/33 MHz
1010_001
100 MHz
2
200 MHz
2.5
250 MHz
3/6
66/33 MHz
1010_010
100 MHz
2
200 MHz
3
300 MHz
3/6
66/33 MHz
1010_011
100 MHz
2
200 MHz
3.5
350 MHz
3/6
66/33 MHz
1010_100
100 MHz
2
200 MHz
4
400 MHz
3/6
66/33 MHz
1011_000
100 MHz
2.5
250 MHz
2
200 MHz
4/8
62/31 MHz
1011_001
100 MHz
2.5
250 MHz
2.5
250 MHz
4/8
62/31MHz
1011_010
100 MHz
2.5
250 MHz
3
300 MHz
4/8
62/31 MHz
1011_011
100 MHz
2.5
250 MHz
3.5
350 MHz
4/8
62/31 MHz
1011_100
100 MHz
2.5
250 MHz
4
400 MHz
4/8
62/31 MHz
Table 17.
Clock Configuration Modes in PCI Host Mode (Continued)
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