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參數(shù)資料
| 型號： | PC826 |
| 廠商： | Sharp Corporation |
| 英文描述： | Hgh -w=der Vtige, Hgh Density Mounting Type Photocoupler |
| 中文描述： | 杭州到瓦特\u003d德Vtige，生長激素密度安裝類型光電耦合 |
| 文件頁數(shù)： | 1/59頁 |
| 文件大?。?/td> | 455K |
| 代理商： | PC826 |
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1
5336A–HIREL–08/03
Features
PC603e
Microprocessor (Embedded PowerPC
Core) at 133 - 300 MHz
– 280 MIPS at 200 MHz (Dhrystone 2.1)
– 520 MIPS at 300 MHz (Dhrystone 2.1)
– High-performance, Superscalar Microprocessor
– Disable CPU Mode
– Improved Low-power Core
– 16-Kbyte Data and 16-Kbyte Instruction Cache, Four-way Set Associative
– Memory Management Unit (MMU)
– Floating Point Unit (FPU)
– Common On-chip Processor (COP)
Two Bus Architectures: One 64-bit PowerPC and One 32-bit PCI or Local Bus
System Integration Unit (SIU)
– Memory Controller, Including Two Dedicated SDRAM Machines
– PCI up to 66 MHz
– Hardware Bus Monitor and Software Watchdog Timer
– IEEE 1149.1 JTAG Test Access Port
High-performance Communications Processor Module (CPM)
– CPM Frequency Up to 200 MHz
– PowerPC and CPM May Run at Different Frequencies
– Parallel I/O Registers
– On-board 32 KBytes of Dual-port RAM
– Two Multi-channel Controllers (MCCs) Each Supporting 128 Full-duplex, 64-Kbps,
HDLC Lines
– Virtual DMA Functionality
– 3 FCCs Supporting:
Up to 155 Mbps ATM SAR, Maximum of Two (AAL0, AAL1, AAL2, AAL5)
10/100 Mbps Ethernet, Up to Three (IEEE 802.3X with Flow Control)
45 Mbps HDLC/Transparent (Up to Three)
Two UTOPIA Level-2 Master/Slave Ports, Both with Multi-PHY Support. One Can
Support 8/16 bit Data
Three MII Interfaces
Eight TDM Interfaces (T1/E1), Two TDM Ports Can Be Glueless to T3/E3
Power Consumption: 2.5W at 300 MHz
Description
The PC8265A PowerQUICC II
is a versatile communications processor that inte-
grates on one chip, a high-performance PowerPC (PC603e) RISC microprocessor, a
highly flexible system integration unit, and many communications peripheral control-
lers that can be used in a variety of applications, particularly in communications and
networking systems.
The core is an embedded variant of the PC603e microprocessor, specifically referred
to later in this document as the EC603e, with 16 Kbytes of instruction cache and
16 Kbytes of data cache and floating-point unit (FPU). The system interface unit (SIU)
consists of a flexible memory controller that interfaces to almost any user-defined
memory system, a 60x-to-PCI bus bridge and many other peripherals, making this
device a complete system on a chip.
The communications processor module (CPM) includes all the peripherals found in
the PC860, with the addition of three high-performance communication channels that
support new emerging protocols (for example, 155-Mbps ATM and Fast Ethernet).
Equipped with dedicated hardware, the PC8265A can handle up to 256 full-duplex,
time-division, multiplexed logical channels.
PowerPC
-
based
Communications
Processor
PC8265A
PowerQUICC II
Preliminary
Specification
Alpha Site
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