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參數(shù)資料
| 型號： | PC8265A |
| 英文描述： | PC8265A [Updated 9/03. 59 Pages] |
| 中文描述： | PC8265A [更新9 / 03。 59頁] |
| 文件頁數(shù)： | 5/59頁 |
| 文件大?。?/td> | 455K |
| 代理商： | PC8265A |
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5
PC8265A PowerQUICC II
5336A–HIREL–08/03
–
–
Independent transmit and receive routing, frame synchronization
Supports T1, CEPT, T1/E1, T3/E3, pulse code modulation highway, ISDN
basic rate, ISDN primary rate, Motorola interchip digital link (IDL), general
circuit interface (GCI), and user-defined TDM serial interfaces
Eight independent baud rate generators and 20 input clock pins for supplying clocks
to FCCs, SCCs, SMCs, and serial channels
Four independent 16-bit timers that can be interconnected as two 32-bit timers
CPM
32-Kbyte dual-port RAM
Additional MCC host commands
CPM multiplexing
FCC2 can also be connected to the TC layer
PCI bridge
PCI Specification Revision 2.2 compliant and supports frequencies up to 66 MHz
On-chip arbitration
Support for PCI to 60x memory and 60x memory to PCI streaming
PCI Host Bridge or Peripheral capabilities
Includes 4 DMA channels for the following transfers:
–
PCI-to-60x to 60x-to-PCI
–
60x-to-PCI to PCI-to-60x
–
PCI-to-60x to PCI-to-60x
–
60x-to-PCI to 60x-to-PCI
Includes all of the configuration registers (which are automatically loaded from the
EPROM and used to configure the PC8265A) required by the PCI standard as well
as message and doorbell registers
Supports the I2O standard
Hot-Swap friendly (supports the Hot Swap Specification as defined by PICMG 2.1
R1.0 August 3, 1998)
Support for 66 MHz, 3.3V specification
60x-PCI bus core logic which uses a buffer pool to allocate buffers for each port
Makes use of the local bus signals, so there is no need for additional pins
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