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參數(shù)資料
| 型號： | PC8265A |
| 英文描述： | PC8265A [Updated 9/03. 59 Pages] |
| 中文描述： | PC8265A [更新9 / 03。 59頁] |
| 文件頁數(shù)： | 4/59頁 |
| 文件大?。?/td> | 455K |
| 代理商： | PC8265A |
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PC8265A PowerQUICC II
5336A–HIREL–08/03
CPU core can be disabled and the device can be used in slave mode to an external
core
Communications processor module (CPM)
Embedded 32-bit communications processor (CP) uses a RISC architecture for flex-
ible support of communications protocols
Interfaces to G2 core through an on-chip 32-Kbyte dual-port RAM and DMA
controller
Serial DMA channels for receive and transmit on all serial channels
Parallel I/O registers with open-drain and interrupt capability
Virtual DMA functionality executing memory-to-memory and memory-to-I/O
transfers
Three fast communications controllers supporting the following protocols:
–
10/100-Mbit Ethernet/IEEE 802.3 CDMA/CS interface through a media
independent interface (MII)
–
ATM – Full-duplex SAR protocols at 155 Mbps, through UTOPIA interface,
AAL5, AAL1, AAL0 protocols, TM 4.0 CBR, VBR, UBR, ABR traffic types, up
to 16 K external connections
–
Transparent
–
HDLC – Up to T3 rates (clear channel)
Two multichannel controllers (MCCs)
–
Each MCC handles 128 serial, full-duplex, 64-Kbps data channels. Each
MCC can be split into four subgroups of 32 channels each
–
Almost any combination of subgroups can be multiplexed to single or
multiple TDM interfaces up to four TDM interfaces per MCC
Four serial communications controllers (SCCs) identical to those on the PC860,
supporting the digital portions of the following protocols:
–
Ethernet/IEEE 802.3 CDMA/CS
–
HDLC/SDLC and HDLC bus
–
Universal asynchronous receiver transmitter (UART)
–
Synchronous UART
–
Binary synchronous (BISYNC) communications
–
Transparent
Two serial management controllers (SMCs), identical to those of the PC860
–
Provides management for BRI devices as general circuit interface (GCI)
controllers in time-division-multiplexed (TDM) channels
–
Transparent
–
UART (low-speed operation)
One serial peripheral interface identical to the PC860 SPI
One inter-integrated circuit (I2C) controller (identical to the PC860 I2 C controller)
–
Microwire compatible
–
Multiple-master, single-master, and slave modes
Up to eight TDM interfaces
–
Supports two groups of four TDM channels for a total of eight TDMs
–
2,048 bytes of SI RAM
–
Bit or byte resolution
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