參數(shù)資料
型號(hào)： PC8265A
英文描述： PC8265A [Updated 9/03. 59 Pages]
中文描述： PC8265A [更新9 / 03。 59頁(yè)]
文件頁(yè)數(shù)： 44/59頁(yè)
文件大?。?/td> 455K
代理商： PC8265A
44
PC8265A PowerQUICC II
5336A–HIREL–08/03
Figure 11 shows signal behavior for all parity modes (including ECC, RMW parity, and standard parity).
Figure 11.
Parity Mode Diagram
Figure 12 shows signal behavior in MEMC mode.
Figure 12.
MEMC Mode Diagram
Note:
Generally, all PC8265A bus and system output signals are driven from the rising edge of
the input clock (CLKin). Memory controller signals, however, trigger on four points within
a CLKin cycle. Each cycle is divided by four internal ticks: T1, T2, T3, and T4. T1 always
occurs at the rising edge, and T3 at the falling edge, of CLKin. However, the spacing of
T2 and T4 depends on the PLL clock ratio selected, as shown in Table 13.
sp13
sp33b/sp10
sp10
sp10
sp14
CLKin
DATA bus, ECC, and PARITY mode input signals
DP mode input signal
DP mode output signal
Table 13.
Tick Spacing for Memory Controller Signals
PLL Clock Ratio
Tick Spacing (T1 Occurs at the Rising Edge of CLKin)
T2
T3
T4
1:2, 1:3, 1:4, 1:5, 1:6
1/4 CLKin
1/2 CLKin
3/4 CLKin
1:2.5
3/10 CLKin
1/2 CLKin
8/10 CLKin
1:3.5
4/14 CLKin
1/2 CLKin
11/14 CLKin
sp34/sp30
CLKin
V_CLK
Memory controller signals
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